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Harold Dekkers

Publications and source records attributed to Harold Dekkers.

4 recordsLinked to original sources

Revealing the Partially Coherent Nature of Transport in IGZO

Thin-film transistors based on amorphous oxide semiconductors (AOS) are promising candidates for enabling further DRAM scaling and 3D integration, which are critical for advanced computing. Despite extensive research, the charge transport mechanism in these disordered semiconductors remains poorly understood. In this work, we investigate charge transport in the archetypical AOS material, indium gallium zinc oxide (IGZO), across a range of compositions and temperatures using thin-film transistors and Hall bar structures. Our results show that the electrons involved in transport exhibit partially spatial coherence and non-degenerate conduction. Under these conditions, transport is dominated by electron transfer across insulating gaps between locally coherent regions, rather than by degenerate percolative transport above a mobility edge, or by localized-state hopping, both of which are widely assumed in the literature. While fluctuation-induced tunnelling has previously been invoked to describe low-temperature transport in oxide transistors, we show that such behavior originates from partially coherent electronic states and develop a field-effect-aware fluctuation-induced tunnelling (FEAFIT) framework that explicitly accounts for gate modulation of the tunneling landscape. The FEAFIT model accurately predicts experimental data across all compositions, temperatures, and gate voltages, enabling extraction of fundamental transport parameters. These tunnelling parameters are then correlated with electron coherence dimensions and the degree of energetic disorder obtained from first-principles calculations. Our findings advance the fundamental understanding of charge transport in AOS-based transistors and provide a foundation for further performance improvements

cond-mat.mtrl-sci

Subthreshold Swing Behavior in Amorphous Indium-Gallium-Zinc-Oxide Transistors from Room to Cryogenic Temperatures

While cryogenic-temperature subthreshold swing (SS) in crystalline semiconductors has been widely studied, a careful study on the temperature-dependent SS in amorphous oxide semiconductors remains lacking. In this paper, a comprehensive analysis of the SS in thin-film transistors with an amorphous indium gallium zinc oxide (IGZO) channel at temperatures from 300 K down to 4 K is presented. Main observations include: 1) At room temperature (300 K), the devices exhibit a SS of 61 mV/dec, and a low interface trap density (<1011 cm-2), among the best reported values for IGZO devices. 2) A SS saturation around 40 mV/dec is observed between 200 K and 100 K. It is well explained by the electron transport via band tail states with exponential decay (Wt) of 13 meV. 3) At deep-cryogenic temperature, SS increase significantly exceeding 200 mV/dec at 4 K. Such high SS values are actually limited by the measurement current range, confirmed by Id-Vg simulations based on the variable range hopping (VRH) model. This work not only elucidates the SS behavior in amorphous IGZO devices but also provides a deep understanding of the physical mechanisms of electron transport in amorphous semiconductors.

cond-mat.mtrl-sci

The impact of process steps on nearly ideal subthreshold slope in 300-mm compatible InGaZnO TFT

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) ~ 60 mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T = 4 K - 300 K) and multi-frequency (f = 1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

physics.app-ph

Sub-40mV Sigma-VTH IGZO nFETs in 300mm Fab

Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively leveraging 300mm fab processing. While the passivation of oxygen vacancies in IGZO is challenging with an integration of front side gate, a scaled back gated flow has been optimized by multiplying design of experiments around contacts and material engineering. We then successfully demonstrated sub-40mV $σ$(VTH_ON) in scaled IGZO nFETs. Regarding the performance and the VTH_ON control, a new IGZO phase is also reported. A model of dopants location is proposed to better explain the experimental results reported in literature.

cond-mat.mtrl-sci