arXiv subjects

Hiu Yung Wong

Publications and source records attributed to Hiu Yung Wong.

At least 19 recordsLinked to original sources

arXiv2026

AI and TCAD for Inverse Design and Defect Discovery: From Simple Machine Learning to LLM

AI has revolutionized various engineering domains, but its impact on semiconductor device design and defect discovery is still limited, due to limited data and the curse of dimensionality. In this paper, we will discuss our work on using the Technology Computer-Aided-Design (TCAD) to generate precise data needed for machine learning (ML) to enable simulation-augmented ML. We demonstrate that with minimal domain expertise, it is possible to create a machine that performs as well as a device engineer on a specific task. We will show that auto-encoder-based machine learning models and noise engineering applied to TCAD data are effective at learning latent physics, and that the models can be seamlessly applied to experimental data. We will demonstrate how to build a device-engineer-level model step by step through various examples, including using only non-destructive electrical data to inverse-engineer the PiN diode layer thickness variations, the Ga2O3 Schottky diode doping and anode workfunction variations, and the transistor contact resistance in an inverter. Examples also include the generation of a FinFET IV/CV prediction model, the mapping between transistor images and IV curves, and the automatic calibration of TCAD parameters for a Ga2O3 Schottky diode, which can only be handled well by experienced TCAD engineers. Finally, to fully realize the potential of AI, large language models (LLMs) and multimodal LLMs (MLLMs) are believed to be necessary. We will discuss the application of LLMs to TCAD command file creation and our vision for MLLMs in automated device design and defect discovery.

cs.LG↗

arXiv2026

TCAD Cryogenic Model Parameters Calibration based on 65 nm NMOS Experimental Data

In this paper, 65 nm n-type Metal-Oxide-Semiconductor Field-Effect-Transistors (nMOSFETs) are taped out and measured at 292 K to 4.5 K. Technology Computer-Aided-Design (TCAD) model parameters are then calibrated to fit the simulation curves to experimental electrical curves. Transmission electron microscopy (TEM) is used to unveil the dimensions of the transistors to ensure accurate modeling. The experimental and simulation capacitance-voltage (CV) curves, drain current - gate voltage (IDVG) curves, and drain current - drain voltage (IDVD) curves are fitted well using the calibrated parameters. The major models calibrated are the Lucent model, which is comprised of an extended PhuMob model, Lombardi model for surface mobility, and the Hänsch high field mobility model. A band-tail model with adjusted band width is applied to fit the sub-threshold swings at all temperatures. The calibrated parameters are expected to be applicable to other technologies because TCAD models are not technology-specific. It is also found that, except for saturation velocity, no new temperature-dependent model is needed. The calibration process and fitting strategies are detailed and are expected to be applicable to calibrate other transistor types.

physics.comp-ph↗

arXiv2026

A Novel Parallel QCNN Architecture with Efficient Classical Simulability

This work presents a study of an implementation of a novel Quantum Convolutional Neural Network (QCNN) for binary classification of images from the Modified National Institute of Standards and Technology (MNIST) dataset. Using a novel architecture inspired by previous QCNN and classical convolutional neural network (CNN) implementations, we use a hierarchical partitioning approach to implement a QCNN circuit that can be approximated and simulated efficiently on a classical machine for a large problem. First, the original image is partitioned such that each process handles a smaller portion of the image, which is encoded into independent states. Then, these partitions merge and combine, resulting in states that contain information from both partitions while halving the number of processes. After repeating this until one process remains, we reduce the dimensionality of the state until a single qubit remains for measurement. Using this approach, we can use multiple processes in parallel to simulate a large QCNN program without the need for exponentially growing hardware requirements as the number of qubits increases. In our work, we use this scheme to train a 128-qubit model, which is impossible to run on any classical supercomputer without the novel architecture. We also explore the impact of this new model architecture on prediction accuracy by training it to perform binary classification on the MNIST dataset with a small number of qubits, and comparing it to a model without partitioning. Our initial findings show that partitioning images into smaller sub-images with this architecture does not degrade the model's performance and sometimes even improves it, likely because it reduces the Barren plateaus issue in the partitioning process.

quant-ph↗

arXiv2026

Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques

In this work, 3D full-domain 3 nm gate-all-around field-effect transistor (GAA-FET) static random access memories (SRAMs) with various substrate isolation techniques are simulated using Technology Computer-Aided Design (TCAD). In addition to the traditional bottom dielectric isolation (BDI), which isolates the source/drain (S/D) from the substrate (dubbed SDBDI), and the punch-through stopper (PTS), a novel channel-BDI (C-BDI) is proposed, allowing S/D-to-substrate connection. The self-heating effect and radiation hardness due to various isolation techniques are studied. It is found that, firstly, the increase in self-heating due to BDI is negligible. Secondly, in the novel CBDI, even without PTS, the increase in leakage current IOFF is minimal. Thirdly, for SD-BDI with underlap (to minimize stress relaxation), while IOFF increases, the static noise margin (SNM) remains unchanged and robust against single-event upset (SEU) even if the underlap is as much as 20 nm. Finally, all structures are immune to the alpha-particle SEU, and BDI enhances the radiation hardness substantially. Moreover, radiation hardness is insensitive to BDI thickness.

cs.ET↗

arXiv2026

Simulation of Two-qubit Gate Variability and Fidelity of Spin Qubits Built on Nanosheet Technology

Silicon spin qubits are promising for large-scale quantum-computer integration because they can fully leverage the well-developed semiconductor infrastructure. However, the low fidelity of two-qubit entanglement gates remains a key barrier to large-scale integrations. Recent simulations of silicon spin-qubit two-qubit gates have been performed on silicon-on-insulator (SOI) platforms, while nanosheet-based charge-qubit work has been limited to single-qubit operation using a two-dimensional Schrödinger approximation. In this work, we study silicon spin-qubit double quantum dots built on nanosheet technology using the Quantum Technology Computer-Aided Design (QTCAD) simulation suite to run three-dimensional Poisson and Schroedinger solvers, followed by a many-body solver to extract exchange interactions. We evaluate the exchange energy sensitivity to process and bias variations and then use QuTiP to solve the master equation for a two-qubit gate. The results show that millivolt-level bias variations at the plunger and middle barrier gates can reduce the gate fidelity below 99%, a common threshold target for many fault-tolerant quantum-computing algorithms. Gate-referred 1/f charge-noise effects are also analyzed through the resulting coherence time.

quant-ph↗

arXiv2026

Review of Superconducting Qubit Devices and Their Large-Scale Integration

The superconducting qubit quantum computer is one of the most promising quantum computing architectures for large-scale integration due to its maturity and close proximity to the well-established semiconductor manufacturing infrastructure. From an education perspective, it also bridges classical microwave electronics and quantum electrodynamics. In this paper, we will review the basics of quantum computers, superconductivity, and Josephson junctions. We then introduce important technologies and concepts related to DiVincenzo's criteria, which are the necessary conditions for the superconducting qubits to work as a useful quantum computer. Firstly, we will discuss various types of superconducting qubits formed with Josephson junctions, from which we will understand the trade-off across multiple design parameters, including their noise immunity. Secondly, we will discuss different schemes to achieve entanglement gate operations, which are a major bottleneck in achieving more efficient fault-tolerant quantum computing. Thirdly, we will review readout engineering, including the implementations of the Purcell filters and quantum-limited amplifiers. Finally, we will discuss the nature and review the studies of two-level system defects, which are currently the limiting factor of qubit coherence time. DiVincenzo's criteria are only the necessary conditions for a technology to be eligible for quantum computing. To have a useful quantum computer, large-scale integration is required. We will review proposals and developments for the large-scale integration of superconducting qubit devices. By comparing with the application of electronic design automation (EDA) in semiconductors, we will also review the use of EDA in superconducting qubit quantum computer design, which is necessary for its large-scale integration.

quant-ph↗

arXiv2025

Ga$_2$O$_3$ TCAD Mobility Parameter Calibration using Simulation Augmented Machine Learning with Physics Informed Neural Network

In this paper, we demonstrate the feasibility of performing automatic Technology Computer Aided Design (TCAD) parameter calibration and extraction using machine learning, with the machine trained solely by TCAD simulation data. The methodology is validated using experimental data. Schottky Barrier Diodes (SBDs) with different effective anode workfunction (WF) are fabricated with emerging ultra-wide bandgap material, Gallium Oxide (Ga2O3), and are measured at various temperatures (T). Their current voltage curves are used for automatic Ga2O3 Philips Unified Mobility (PhuMob) model parameters calibration. Five critical PhuMob parameters were calibrated. The machine consists of an autoencoder and a neural network and is trained solely by TCAD simulation data with variations in WF, T, and the five PhuMob parameters (seven variations in total). Then, Ga2O3 PhuMob parameters are extracted from the noisy experimental curves. Subsequent TCAD simulation using the extracted parameters shows that the quality of the parameters is as good as an expert's calibration at the pre-turned on regime, but not in the on state regime. By using a simple physics-informed neural network, the machine performs as well as the human expert in all regimes.

cs.LG↗

arXiv2025

Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design

In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design a static random-access memory (SRAM) using gate-all-around field-effect-transistor (GAA-FET) technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LETmax, for the alpha particle in Si and Si$_x$Ge$_{1-x}$. Based on that, by designing a sub-7nm GAA-FET-based SRAM with bottom dielectric isolation (BDI), we show that the SRAM does not flip even if the particle strike is in the worst-case scenario.

cs.ET↗

arXiv2025

Application of Machine Learning for Correcting Defect-induced Neuromorphic Circuit Inference Errors

This paper presents a machine learning-based approach to correct inference errors caused by stuck-at faults in fully analog ReRAM-based neuromorphic circuits. Using a Design-Technology Co-Optimization (DTCO) simulation framework, we model and analyze six spatial defect types-circular, circular-complement, ring, row, column, and checkerboard-across multiple layers of a multi-array neuromorphic architecture. We demonstrate that the proposed correction method, which employs a lightweight neural network trained on the circuit's output voltages, can recover up to 35% (from 55% to 90%) inference accuracy loss in defective scenarios. Our results, based on handwritten digit recognition tasks, show that even small corrective networks can significantly improve circuit robustness. This method offers a scalable and energy-efficient path toward enhanced yield and reliability for neuromorphic systems in edge and internet-of-things (IoTs) applications. In addition to correcting the specific defect types used during training, our method also demonstrates the ability to generalize-achieving reasonable accuracy when tested on different types of defects not seen during training. The framework can be readily extended to support real-time adaptive learning, enabling on-chip correction for dynamic or aging-induced fault profiles.

cs.NE↗

arXiv2025

Quantum Computing Architecture and Hardware for Engineers -- Step by Step -- Volume II

After publishing my book "Quantum Computing Architecture and Hardware for Engineers: Step by Step" [1] (now I call it Volume I), in which spin qubit and superconducting qubit quantum computers were covered, I decided to continue to write the second volume to cover the trapped ion qubit quantum computer, which was also taught in my EE274 class. I follow the same structure as in Volume I by discussing the physics, mathematics, and their connection to laser pulses and electronics based on how they fulfill the five DiVincenzo's criteria. I also think it would be a good idea to share the second volume on arXiv so that more people can read it for free, and I can continue to update the contents. As of July 2025, I have finished the trapped ion quantum computer part. In the future, I plan to write more critical topics in a step-by-step manner to bridge engineers who did not receive rigorous training in Physics to the quantum computing world.

quant-ph↗

arXiv2025

Analysis of a 3D Integrated Superconducting Quantum Chip Structure

This work presents a combined analytical and simulation-based study of a 3D-integrated quantum chip architecture. We model a flip-chip-inspired structure by stacking two superconducting qubits fabricated on separate high-resistivity silicon substrates through a dielectric interlayer. Utilizing \emph{rigorous} Ansys High-Frequency Structure Simulator (HFSS) simulations and analytical models from microwave engineering and quantum theory, we evaluate key quantum metrics such as eigenfrequencies, Q-factors, decoherence times, anharmonicity, cross-Kerr, participation ratios, and qubit coupling energy to describe the performance of the quantum device as a function of integration parameters. The integration parameters include the thickness and the quality of the dielectric interlayer. For detuned qubits, these metrics remain mostly invariant with respect to the substrate separation. However, introducing dielectric interlayer loss decreases the qubit quality factor, which consequentially degrades the relaxation time of the qubit. It is found that for the structure studied in this work, the stacked chip distance can be as small as $0.5 \text{mm}$. These findings support the viability of 3D quantum integration as a scalable alternative to planar architectures, while identifying key limitations in qubit coherence preservation due to lossy interlayer materials.

quant-ph↗

arXiv2024

Physics-Informed Neural Network for Predicting Out-of-Training-Range TCAD Solution with Minimized Domain Expertise

Machine learning (ML) is promising in assisting technology computer-aided design (TCAD) simulations to alleviate difficulty in convergence and prolonged simulation time. While ML is widely used in TCAD, they either require access to the internal solver, require extensive domain expertise, are only trained by terminal quantities such as currents and voltages, and/or lack out-of-training-range prediction capability. In this paper, using Si nanowire as an example, we demonstrate that it is possible to use a physics-informed neural network (PINN) to predict out-of-training-range TCAD solutions without accessing the internal solver and with minimal domain expertise. The machine not only can predict a 2.5 times larger range than the training but also can predict the inversion region by only being trained with subthreshold region data. The physics-informed module is also trained with data without the need for human-coded equations making this easier to be extended to more sophisticated systems.

cs.LG↗

arXiv2024

Stuck-at Faults in ReRAM Neuromorphic Circuit Array and their Correction through Machine Learning

In this paper, we study the inference accuracy of the Resistive Random Access Memory (ReRAM) neuromorphic circuit due to stuck-at faults (stuck-on, stuck-off, and stuck at a certain resistive value). A simulation framework using Python is used to perform supervised machine learning (neural network with 3 hidden layers, 1 input layer, and 1 output layer) of handwritten digits and construct a corresponding fully analog neuromorphic circuit (4 synaptic arrays) simulated by Spectre. A generic 45nm Process Development Kit (PDK) was used. We study the difference in the inference accuracy degradation due to stuck-on and stuck-off defects. Various defect patterns are studied including circular, ring, row, column, and circular-complement defects. It is found that stuck-on and stuck-off defects have a similar effect on inference accuracy. However, it is also found that if there is a spatial defect variation across the columns, the inference accuracy may be degraded significantly. We also propose a machine learning (ML) strategy to recover the inference accuracy degradation due to stuck-at faults. The inference accuracy is improved from 48% to 85% in a defective neuromorphic circuit.

cs.AR↗

arXiv2023

Device Image-IV Mapping using Variational Autoencoder for Inverse Design and Forward Prediction

This paper demonstrates the learning of the underlying device physics by mapping device structure images to their corresponding Current-Voltage (IV) characteristics using a novel framework based on variational autoencoders (VAE). Since VAE is used, domain expertise is not required and the framework can be quickly deployed on any new device and measurement. This is expected to be useful in the compact modeling of novel devices when only device cross-sectional images and electrical characteristics are available (e.g. novel emerging memory). Technology Computer-Aided Design (TCAD) generated and hand-drawn Metal-Oxide-Semiconductor (MOS) device images and noisy drain-current-gate-voltage curves (IDVG) are used for the demonstration. The framework is formed by stacking two VAEs (one for image manifold learning and one for IDVG manifold learning) which communicate with each other through the latent variables. Five independent variables with different strengths are used. It is shown that it can perform inverse design (generate a design structure for a given IDVG) and forward prediction (predict IDVG for a given structure image, which can be used for compact modeling if the image is treated as device parameters) successfully. Since manifold learning is used, the machine is shown to be robust against noise in the inputs (i.e. using hand-drawn images and noisy IDVG curves) and not confused by weak and irrelevant independent variables.

cs.LG↗

arXiv2023

Step-by-Step HHL Algorithm Walkthrough to Enhance the Understanding of Critical Quantum Computing Concepts

After learning basic quantum computing concepts, it is desirable to reinforce the learning using an important and relatively complex algorithm through which the students can observe and appreciate how the qubits evolve and interact with each other. Harrow-Hassidim-Lloyd (HHL) quantum algorithm, which can solve Linear System Problems with exponential speed-up over the classical method and is the basic of many important quantum computing algorithms, is used to serve this purpose. The HHL algorithm is explained analytically followed by a 4-qubit numerical example in bra-ket notation. Matlab code corresponding to the numerical example is available for students to gain a deeper understanding of the HHL algorithm from a pure matrix point of view. A quantum circuit programmed using qiskit is also provided which can be used for real hardware execution in IBM quantum computers. After going through the material, students are expected to have a better appreciation of the concepts such as basis transformation, bra-ket and matrix representations, superposition, entanglement, controlled operations, measurement, Quantum Fourier Transformation, Quantum Phase Estimation, and quantum programming. To help readers review these basic concepts, brief explanations augmented by the HHL numerical examples in the main text are provided in the Appendix.

quant-ph↗

arXiv2022

Vertical GaN Diode BV Maximization through Rapid TCAD Simulation and ML-enabled Surrogate Model

In this paper, two methodologies are used to speed up the maximization of the breakdown volt-age (BV) of a vertical GaN diode that has a theoretical maximum BV of ~2100V. Firstly, we demonstrated a 5X faster accurate simulation method in Technology Computer-Aided-Design (TCAD). This allows us to find 50% more numbers of high BV (>1400V) designs at a given simulation time. Secondly, a machine learning (ML) model is developed using TCAD-generated data and used as a surrogate model for differential evolution optimization. It can inversely design an out-of-the-training-range structure with BV as high as 1887V (89% of the ideal case) compared to ~1100V designed with human domain expertise.

cs.LG↗

arXiv2022

A Simulation Methodology for Superconducting Qubit Readout Fidelity

Qubit readout is a critical part of any quantum computer including the superconducting-qubit-based one. The readout fidelity is affected by the readout pulse width, readout pulse energy, resonator design, qubit design, qubit-resonator coupling, and the noise generated along the readout path. It is thus important to model and predict the fidelity based on various design parameters along the readout path. In this work, a simulation methodology for superconducting qubit readout fidelity is proposed and implemented using Matlab and Ansys HFSS to allow the co-optimization in the readout path. As an example, parameters are taken from an actual superconducting-qubit-based quantum computer and the simulation is calibrated to one experimental point. It is then used to predict the readout error of the system as a function of readout pulse width and power and the results match the experiment well. It is found that the system can still maintain high fidelity even if the input power is reduced by 7dB or if the readout pulse width is 40% narrower. This can be used to guide the design and optimization of a superconducting qubit readout system.

quant-ph↗

arXiv2022

A Wide Temperature Range Unified Undoped Bulk Silicon Electron and Hole Mobility Model

For decades, there is no unified model developed for Silicon carriers from 4K to above room temperature. In this paper, a unified undoped Silicon low field and high field mobility model for both electron in the <100> and <111> directions from 8K to 300K and 430K, respectively, and hole in the <100> direction from 6K to 430K is proposed and calibrated to the experiment. It is found that the Canali high field saturation model is sufficient to fit the <111> experimental data but not the <100> data due to the anisotropy-induced negative differential velocity. Therefore, a modified Farahmand model is used. To allow parameter interpolation in anisotropic simulation, the modified Farahmand model is also calibrated for the <111> direction. The model is then used to predict the mobility of electrons and holes in undoped Si at 4K, which can be served as the initial calibration parameters when reliable experimental data is available for the TCAD model development.

physics.comp-ph↗