arXiv subjects

Hiu Yung Wong

Publications and source records attributed to Hiu Yung Wong.

21 records · Page 2Linked to original sources

arXiv2022

FinFET and Nanowire SRAM Radiation Hardness Studies using Ab initio-TCAD Simulation Framework

In this paper, we study the vulnerability of 5nm node FinFET and nanowire (20nm gate length) and their corresponding SRAM under radiation. Ab initio tools, SRIM, PHITS, and GEANT4, are used to find the Linear Energy Transfer (LET) of neutron and alpha particles in Silicon and Silicon-Germanium. Technology Computer-Aided Design (TCAD) is then used to find the most vulnerable incident location and direction in FinFET, nanowire, and their SRAM. Full 3D TCAD simulation, which allows the study of layout effect in SRAM, is used. It is found that NW is about 2-3 times more robust than FinFET in terms of flipping energy. Based on the simulation in the ab initio-TCAD framework, it is projected that there is a possibility to design an SRAM using NW that is immune to alpha-particle. It is also expected that SRAM can be optimized for more robust radiation hardness if Design Technology Co-Optimization (DTCO) is taken into consideration.

cond-mat.mtrl-sci↗

arXiv2021

TCAD Modeling of Cryogenic nMOSFET ON-State Current and Subthreshold Slope

In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided Design (TCAD). The device used is a 0.35um technology nMOSFET with W/L=10um/10um. We show that it is possible to model the abnormal SS by using interface acceptor traps with a density less than 2e12cm-2. We also propose trap distribution profiles in the energy space that can be used to reproduce other observed SS from 4K to 300K. Although this work does not prove or disprove any possible origin of the abnormal SS, it shows that one cannot completely rule out the interfacial traps as the origin and it shows that interfacial traps can be used to model the abnormal SS before the origin is fully understood. We also show that Drain-Induced-Barrier-Lowering (DIBL) is much reduced at cryogenic temperature due to the abnormal slope and the device optimization strategy might need to be revised.

physics.comp-ph↗

arXiv2021

Study of using Quantum Computer to Solve Poisson Equation in Gate Insulators

In this paper, the application of quantum computing (QC) in solving gate insulator Poisson equation is studied, through QC simulator and hardware in IBM. Various gate insulator stacks with and without fixed charges are studied. It is found that by increasing the number of clock bits and by choosing appropriate evolution time, accurate solutions can be obtained in QC simulation. However, when the real quantum hardware is used, the accuracy is substantially reduced. Therefore, a more robust quantum circuit or error correction should be employed and developed.

quant-ph↗