arXiv subjects

III.

Publications and source records attributed to III..

3 recordsLinked to original sources

arXiv2024

MKIDGen3: Energy-Resolving, Single-Photon-Counting MKID Readout on an RFSoC

Building large, cryogenic MKID arrays requires processing highly-multiplexed, wideband readout signals in real time; a task that has previously required large, heavy, and power-intensive custom electronics. In this work, we present the third-generation UVOIR MKID readout system (Gen3) which is capable of reading out twice as many detectors with a fifth the weight and power and an order of magnitude less volume and cost-per-pixel as compared to the previous system. Gen3 leverages the Xilinx RFSoC4x2 platform to read out 2048, 1 MHz MKID channels per board. The system takes a modern approach to FPGA design using Vitis High-Level Synthesis (HLS) to specify signal processing blocks in C/C++, Vivado ML Intelligent Design Runs (IDR) to inform implementation stragety and close timing, and Python Productivity for ZYNQ (PYNQ) to simplify interacting with and programming the FPGA using Python. This design suite and tool flow allows general users to contribute to and maintain the design and positions Gen3 to rapidly migrate to future platforms as they become available. In this work, we describe the system requirements, design, and implementation. We also provide performance characterization details and show that the system achieves detector-limited resolving power in the case of few readout tones and minimal degradation with all 2048 tones. Planned upgrades and future work are also discussed. The Gen3 MKID readout system is fully open-source and is expected to facilitate future array scaling to megapixel-sized formats and increase the feasibility of deploying UVOIR MKIDs in space.

physics.ins-det↗

arXiv2022

Highly-Multiplexed Superconducting Detector Readout: Approachable High-Speed FPGA Design

This work presents the design and preliminary performance of a highly-multiplexed superconducting detector readout. The readout system is implemented on the Xilinx ZCU111 RFSoC Evaluation Board. The current design uses 12% of the DSPs, 60% of the LUTs, 20% of the FFs, and 30% of the BRAM and makes timing at 512 MHz. The system uses two integrated ADCs and DACs running at 4.096 GSPS to read out 2,048 superconducting detectors. This work targets a 2x increase in the number of superconducting detectors processed per board with 80% less power than previous readout schemes. The open-source design leverages modern FPGA productivity tools including Vivado High-Level Synthesis to create all custom IP blocks, PYNQ to test and verify individual IP and develop Python drivers, and Vivado ML Intelligent Design Runs to close timing. We emphasize strategies for achieving timing closure without custom HDL which we expect to be useful for superconducting device groups looking to utilize FPGAs in high-performance applications without specialized knowledge in FPGA design.

astro-ph.IM↗

arXiv2020

A direct interferometric test of the nonlinear phase shift gate

We propose a direct interferometric test of the Non-Linear Phase Shift Gate (NLPSG), an essential piece of a Knill Laflamme Milburn Contolled-NOT (KLM CNOT) gate. We develop our analysis for the both the case of the original, bulk optical KLM NLPSG and for the scalable integrated nano-photonic NLPSG based on Micro-Ring Resonators (MRRs) that we have proposed very recently. Specifically, we consider the interference between the target photon mode of the NLPSG along one arm of a Mach Zehnder Interferometer (MZI) and a mode subject to an adjustable linear phase along the other arm. Analysis of triple-photon coincidences between the two modes at the output of the MZI and the success ancillary mode of the NLPSG provides a signature of the operation of the NLPSG. We examine the triple coincidence results for experimentally realistic cases of click/no-click detection with sub-unity detection efficiencies. Further we compare the case for which the MZI input modes are seeded with weak Coherent States (w-CS) and to that for which the input states are those resulting from colinear Spontaneous Parametric Down Conversion (cl-SPDC). In particular, we show that, though more difficult to prepare, cl-SPDC states offer clear advantages for performing the test, especially in the case of relatively low photon detector efficiency.

quant-ph↗