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Ikuo Kurachi

Publications and source records attributed to Ikuo Kurachi.

24 records · Page 2Linked to original sources

Development FD-SOI MOSFET amplifiers for integrated read-out circuit of superconducting-tunnel-junction single-photon-detectors

We proposed a new high resolution single photon infrared spectrometer for search for radiative decay of cosmic neutrino background(C$ν$B). The superconducting-tunnel-junctions(STJs) are used as a single photoncounting device. Each STJ consists of Nb/Al/Al${}_{\mathrm{x}}$O${}_{\mathrm{y}}$/Al/Nb layers and their thicknesses are optimized for the operation temperature at 370 mK cooled by a ${}^{3}$He sorption refrigerator. Our STJs achieved the leak current 250 pA and the measured data implies that a smaller area STJ fulfills our requirement. FD-SOI MOSFETs are employed to amplify the STJ signal current in order to increase signal-to-noise ratio(S/N). FD-SOI MOSFETs can be operated at cryogenic temperature of 370 mK, which reduces the noise of the signal amplification system. FD-SOI MOSFET characteristics are measured at cryogenic temperature. The Id-Vgs curve shows a sharper turn on with a higher threshold voltage and the Id-Vds curve shows a non linear shape in linear region at cryogenic temperature. Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors. The bias voltage for STJ detectors are 0.4 mV and it must be well stabilized to deliver high performance. We proposed an FD-SOI MOSFET based charge integrated amplifier design as a read-out circuit of STJ detectors. The requirements for an operational amplifier used in the amplifier is estimated using SPICE simulation. The op-amp required to have a fast response(GBW$\geq$100 MHz) and it must have low power dissipation as compared to the cooling power of refrigerator.

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Development of the Pixelated Photon Detector Using Silicon on Insulator Technology for TOF-PET

To measure light emission pattern in scintillator, higher sensitivity and faster response are required to photo detector. Such as single photon avalanche diode (SPAD), conventional pixelated photo detector is operated at Geiger avalanche multiplication. However higher gain of SPAD seems very attractive, photon detection efficiency per unit area is low. This weak point is mainly caused by Geiger avalanche mechanism. To overcome these difficulties, we designed Pixelated Linear Avalanche Integration Detector using Silicon on Insulator technology (SOI-Plaid). To avoid dark count noise and dead time comes from quench circuit, we are planning to use APD in linear multiplication mode. SOI technology enables laminating readout circuit and APD layer, and high-speed and low-noise signal reading regardless smaller gain of linear APD. This study shows design of linear APD by using SOI fabrication process. We designed test element group (TEG) of linear APD and inspected optimal structure of linear APD.

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Compensation for TID Damage in SOI Pixel Devices

We are investigating adaption of SOI pixel devices for future high energy physic(HEP) experiments. The pixel sensors are required to be operational in very severe radiation environment. Most challenging issue in the adoption is the TID (total ionizing dose) damage where holes trapped in oxide layers affect the operation of nearby transistors. We have introduced a second SOI layer - SOI2 beneath the BOX (Buried OXide) layer - in order to compensate for the TID effect by applying a negative voltage to this electrode to cancel the effect caused by accumulated positive holes. In this paper, the TID effects caused by Co gamma-ray irradiation are presented based on the transistor characteristics measurements. The irradiation was carried out in various biasing conditions to investigate hole accumulation dependence on the potential configurations. We also compare the data with samples irradiated with X-ray. Since we observed a fair agreement between the two irradiation datasets, the TID effects have been investigated in a wide dose range from 100~Gy to 2~MGy.

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Characteristics of Non-Irradiated and Irradiated Double SOI Integration Type Sensor

We are developing monolithic pixel sensors based on a 0.2 $μ$m fully-depleted Silicon-on-Insulator (SOI) technology for HEP experiment applications. The total ionizing dose (TID) effect is the major issue in the applications for hard radiation environments in HEP experiments. To compensate for TID damage, we have introduced a Double SOI structure which has a Middle Silicon layer (SOI2 layer) in addition. We studied the recovery from TID damage induced by $\mathrm{^{60}Co}~γ$'s and other characteristics of an Integration-type Double SOI sensor. The Double SOI sensor irradiated to 100 kGy showed a response for IR laser similar to of a non-irradiated sensor when we applied a negative voltage to the SOI2 layer. We conclude that the Double SOI sensor is radiation hard enough to be used in HEP experiments in harsh radiation environments such as at Bell II or ILC.

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Compensation of radiation damages for SOI pixel detector via tunneling

We are developing monolithic pixel detectors based on SOI technology for high energy physics, X-ray applications and so on.To employ SOI pixel detector on such radiation environments, we have to solve effects of total ionizing dose (TID) for transistors which are enclosed in oxide layer.The holes which are generated and trapped in the oxide layers after irradiation affect characteristics of near-by transistors due to its positive electric field.Annealing and radiation of ultraviolet are not realistic to remove trapped holes for a fabricated detector due to thermal resistance of components and difficulty of handling. We studied compensation of TID effects by tunneling using a high-voltage. For decrease of trapped holes, applied high-voltage to buried p-well which is under oxide layer to inject the electrons into the oxide layer.In this report, recent progress of this study is shown.

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X-ray Radiation Hardness of Fully-Depleted SOI MOSFETs and Its Improvement

X-ray radiation hardness of FD-SOI n- and p-MOSFET has been investigated. After 1.4 kGy(Si) irradiation, 15% drain current increase for n-MOSFET and 20% drain current decrease for p-MOSFET are observed. From analysis of gmmax-Vsub, the major cause of n-MOSFET drain current change is the generated positive charge in BOX. On the other hand, the major cause of p-MOSFET drain current change is the radiation induced gate channel modulation by the generated positive charge in sidewall spacer. It is confirmed that the p-MOSFET drain current change is improved by higher PLDD dose. Thinner BOX is also proposed for further radiation hardness improvement.

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