arXiv subjects

Jan Van Houdt

Publications and source records attributed to Jan Van Houdt.

5 recordsLinked to original sources

arXiv2026

From sLLG to Fokker-Planck: Accurate WER Modeling for Non-Axisymmetric MRAM Devices

The Fokker--Planck (FP) equation is essential for predicting write error rates (WER) in STT and SOT-MRAM devices, but traditional 1D projections fail when symmetry is broken by in-plane fields, field-like torques, or anisotropic barriers. We develop a 2D finite-volume (FVM) solver on the unit sphere and validate it against $10^6$-trajectory stochastic Landau--Lifshitz--Gilbert (sLLG) simulations. The solver supports four discretization schemes---central, Scharfetter--Gummel (SG), upwind, and hybrid adaptive blending---each with different Péclet-dependent accuracy and monotonicity properties. We demonstrate that central differencing recovers ground-truth WER for STT and SOT geometries where 2D effects dominate, and show that the choice of discretization scheme directly affects predicted WER. For magnetic simulations, we recommend hybrid adaptive blending as the optimal balance of accuracy and stability across variable Péclet regimes. These results establish that customizable discretization is critical for accurate, unbiased predictions of switching dynamics in next-generation magnetic memory.

cs.ET↗

arXiv2026

DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) RAMs and hybrid-bonded memory chiplets, and off-chip, monolithically integrated 3D FeNOR storage-class memories (SCMs). For on-chip BEOL RAMs and memory chiplets, we demonstrate the cross-node bitcell footprint scalability of IGZO FeFETs capable of delivering down to 10-A SRAM-equivalent bitcell area ($\sim$0.016 $μ$m$^2$) with 7-nm ground rules while maintaining a sub-5 ns random access latency -- despite their writability challenges. We further identify the sensing margin penalty in NOR FeFET arrays arising from sneak current associated with the negative program-state $V_t$, which requires positive-$V_t$ engineering in order to eliminate the unwanted negative voltage read inhibition -- for example, by ferroelectric layer thinning. Last but not least, we elucidate the read margin implications on 3D FeNOR for SCMs, with the 3D stacking density limited by additional sneak current from neighbor channel shunting.

cs.ET↗

arXiv2025

Subthreshold Swing Behavior in Amorphous Indium-Gallium-Zinc-Oxide Transistors from Room to Cryogenic Temperatures

While cryogenic-temperature subthreshold swing (SS) in crystalline semiconductors has been widely studied, a careful study on the temperature-dependent SS in amorphous oxide semiconductors remains lacking. In this paper, a comprehensive analysis of the SS in thin-film transistors with an amorphous indium gallium zinc oxide (IGZO) channel at temperatures from 300 K down to 4 K is presented. Main observations include: 1) At room temperature (300 K), the devices exhibit a SS of 61 mV/dec, and a low interface trap density (<1011 cm-2), among the best reported values for IGZO devices. 2) A SS saturation around 40 mV/dec is observed between 200 K and 100 K. It is well explained by the electron transport via band tail states with exponential decay (Wt) of 13 meV. 3) At deep-cryogenic temperature, SS increase significantly exceeding 200 mV/dec at 4 K. Such high SS values are actually limited by the measurement current range, confirmed by Id-Vg simulations based on the variable range hopping (VRH) model. This work not only elucidates the SS behavior in amorphous IGZO devices but also provides a deep understanding of the physical mechanisms of electron transport in amorphous semiconductors.

cond-mat.mtrl-sci↗

arXiv2025

The impact of process steps on nearly ideal subthreshold slope in 300-mm compatible InGaZnO TFT

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) ~ 60 mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T = 4 K - 300 K) and multi-frequency (f = 1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

physics.app-ph↗

arXiv2018

Alternative explanation for the steep subthreshold slope in Ferroelectric FETs

Since many years, sub-60mV/decade switching has been reported in ferroelectric FETs. However, thus far these reports have lacked full physical explanation since they typically use a negative capacitance in the ferroelectric layer to be able to explain the experimental observations. Because negative capacitance as such is not a physical concept, we propose an alternative model that relies on the non-linear and non-equilibrium behavior of the ferroelectric layer. It is shown that a steep subthreshold slope can be obtained by a 2-step switching process, referred to as nucleation and propagation. Making use of the concept of domain wall motion as known also from fracture dynamics, we are able to explain the steep slope effect. A simple mathematical model is added to further describe this phenomenon, and to further investigate its eventual benefit for obtaining steep slope transistors in the sub-10nm era.

physics.app-ph↗