arXiv subjects

Jeffrey S. Walling

Publications and source records attributed to Jeffrey S. Walling.

7 recordsLinked to original sources

arXiv2026

A Single-Tuning-Element Loaded Pixelated Tunable Band-Pass Filters with Low Loss via Inverse Synthesis on Massive-Scale Dataset

This paper presents a novel three-phase inverse-design flow for synthesizing tunable pixelated band-pass filters. The workflow consists of: 1) acquisition of a massive dataset ~300000 5-port S-parameter samples using the group's custom electromagnetic solvers accelerated by method-of-moments pre-computation; 2) identification of an initial seed through brute-force search with dataset augmentation by dynamically reassigning the input, output, and tuning ports and randomly applying open or short terminations to the remaining ports; and 3) fine-tuning of the selected seed using a direct-binary-search algorithm. Two design targets are considered: 4G mid-/high-band tunable band-pass filters and 5G n79/UNIII-band tunable band-pass filters. One designed filter achieves a 28% tuning range, with passband peaks reconfigured from 4.64 to 6.16 GHz and insertion loss from 1.3 to 1.8 dB in simulation. All inversely designed filters use only a single varactor, representing the first reported demonstration of continuously reconfigurable inverse design in the microwave regime.

physics.app-ph↗

arXiv2026

236 μW Direct-RF PLL-Free Multi-PSK Transmitter Using Oscillator-Based Phase Synthesis

This paper presents a compact, low-power, direct RF multi-phase-shift keying (PSK) transmitter (TX) that eliminates the need for a phase-locked loop (PLL) by performing phase modulation directly within a ring oscillator. The proposed architecture exploits synchronized charge extraction at the oscillator's transition points to induce controlled phase shifts while maintaining constant amplitude and frequency. A time-domain multi-triggering technique is introduced to enable reconfigurable multi-mode modulation, supporting 16-PSK, 8-PSK, QPSK, and BPSK within a unified hardware structure. The TX circuit is fabricated in a 22-nm FD-SOI process and operates in the ISM band at 2.4 GHz. Measurement results indicate a symbol rate of 2 MSps with a maximum error vector magnitude (EVM) of 5.13% rms. The core TX occupies 23 {\times} 17.6 μm2 and consumes 236 μW, excluding the output driver, which delivers -10 dBm output power over a 60 MHz bandwidth. The proposed design achieves a favorable trade-off between power consumption, circuit complexity, and modulation flexibility, making it well-suited for low-power wireless applications.

eess.SY↗

arXiv2026

Analysis of Edge Mismatch and Output Power Degradation in Cascoded Class-D Power Amplifiers Using Dual-Range Voltage Level Shifters

This paper presents a low-jitter \ac{HVLS} architecture for high-speed mixed-signal and digital power-amplifier applications. The proposed design employs a regenerative cross-coupled feedback network to simultaneously generate two synchronized voltage-domain outputs (e.g., the nominal supply voltage ($V_{\mathrm{DDL}}$) and one at twice its value ($V_{\mathrm{DDH}} = 2V_{\mathrm{DDL}}$)). This enables direct drive of cascoded class-D power amplifiers without additional delay-calibration circuitry, amongst other mixed-signal applications. A prototype \ac{HVLS} circuit, together with an impedance-matching network and a pre-driver for high-speed off-chip characterization, was fabricated in a 22-nm FD-SOI process technology. The total die area, including all interface circuitry, is 477$\times$462~$\mu$m$^{2}$, while the active area of the \ac{HVLS} core is 3.26$\times$2~$\mu$m$^{2}$. Measured at 12.2~GHz, the circuit dissipates 4.43~\textbf{$\mu$W} per switching cycle and achieves an output jitter below 150~fs-rms.

eess.SP↗

arXiv2026

Inverter-Based Differential Amplifiers With Back-Gate Feedback Linearization

Feeding the common-source amplifier output to the back-gate terminal in fully depleted silicon on insulator (FD-SOI) technology exploits the linearizing effect of negative feedback. Analysis and simulation results in 22 nm FD-SOI show that back-gate feedback sets the overall gain approximately independent of the load, contributes no additional noise, and improves linearity by the back-gate voltage gain. Third-order intercept point (IP3) enhancement is at least $60\times$ compared to without feedback in inverter-based, or complementary common-source, differential amplifiers.

eess.SP↗

arXiv2024

Inverse Design of Multi-Layered Manufacturable Pixelated Diplexers Through Optimized Geometrical Configuration and Meshing Strategy in MoM

This paper presents a fast inverse design framework for complex multilayered, multiport pixelated surfaces - a class of structures largely unexplored in current research. Leveraging a method-of-moments (MoM) electromagnetic (EM) solver, the framework enables the rapid synthesis of pixelated device designs. A novel matrix reconstruction technique, based on pre-labeling matrix entries as "inter-pixel" or "inner-pixel," accelerates simulations for each variation of the pixelated structure. To mitigate the cubic increase in computation time associated with additional layers, GPU acceleration is employed. Further enhancing convergence speed, a stochastic multi-pixel flipping search algorithm is integrated into the framework. The effectiveness of this approach is demonstrated through the design of a diplexer achieving a -3-dB bandwidth for one channel spanning 5.23-5.94 GHz and another covering 6.17-7.15 GHz, validated by a full-wave solver.

physics.app-ph↗

arXiv2024

High-Q Slow-Wave Coplanar Waveguides

A comprehensive study of methods of maximizing Q for slow-wave coplanar waveguides is described. In addition to the widths of the signal conductor and coplanar ground lines and the distance between them, the length, spacing and stacking of the metal layers of the substrate shield strips are also shown to be critical in maximizing performance. Measured results from more than 50 different devices show that a 7X increase in the quality factor (e.g., Q > 70 at 24 GHz in 0.18 μm CMOS) is achievable using the optimum topology with optimum dimensions.

physics.app-ph↗

arXiv2020

Multiphase interpolating digital power amplifiers for TX beamforming

This paper presents a 4-channel beamforming TX implemented in 65nm CMOS. Each beamforming TX is comprised of a C-2C split-array multiphase switched-capacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam-steering. This technique is ideal for low-frequency beamforming and MIMO, as it does not require passive or LO based phase shifters. The SCPA is ideal to use as the core element since it can perform frequency translation, data conversion and drive an output at high power and efficiency in a compact die area. A prototype 4-element beamforming TX, occupying 2 mm X 2.5 mm, can achieve peak output power of 24.4 dBm with a peak system efficiency (SE) of 24%, while achieving < 1° phase resolution and <1 dB gain error. When transmitting a 15 MHz, 64 QAM long-term evolution (LTE) signal it outputs 18.4 dBm at 14% SE with a measured adjacent channel leakage ratio (ACLR) < -30 dBc and error vector magnitude (EVM) of 3.27 %-rms at 1.75 GHz. A synthesized beam pattern based on measured results from a single die achieves <0.32°-rms beam angle error and <0.15 dB rms beam amplitude error.

eess.SP↗