arXiv subjects

Jintao Zhang

Publications and source records attributed to Jintao Zhang.

60 records · Page 4Linked to original sources

arXiv2023

Health diagnosis and recuperation of aged Li-ion batteries with data analytics and equivalent circuit modeling

Battery health assessment and recuperation play a crucial role in the utilization of second-life Li-ion batteries. However, due to ambiguous aging mechanisms and lack of correlations between the recovery effects and operational states, it is challenging to accurately estimate battery health and devise a clear strategy for cell rejuvenation. This paper presents aging and reconditioning experiments of 62 commercial high-energy type lithium iron phosphate (LFP) cells, which supplement existing datasets of high-power LFP cells. The relatively large-scale data allow us to use machine learning models to predict cycle life and identify important indicators of recoverable capacity. Considering cell-to-cell inconsistencies, an average test error of $16.84\% \pm 1.87\%$ (mean absolute percentage error) for cycle life prediction is achieved by gradient boosting regressor given information from the first 80 cycles. In addition, it is found that some of the recoverable lost capacity is attributed to the lateral lithium non-uniformity within the electrodes. An equivalent circuit model is built and experimentally validated to demonstrate how such non-uniformity can be accumulated, and how it can give rise to recoverable capacity loss. SHapley Additive exPlanations (SHAP) analysis also reveals that battery operation history significantly affects the capacity recovery.

eess.SP↗

arXiv2022

Temperature sensing using nitrogen-vacancy centers with multiple-poly crystal directions based on Zeeman splitting

We demonstrate a novel method based on the Zeeman splitting of electronic spins to improve the performance for temperature sensing of negatively-charged nitrogen-vacancy (NV) centers in multiple-poly diamond. The theoretical model for selection principle of resonance peaks corresponding to a single NV axis for determining the temperature dependence is clarified. The spectral linewidth is effectively narrowed and the thermometer is insensitive to magnetic field fluctuations. Repeatability and accuracy of the relationship calibration between the zero-field splitting (ZFS) parameter D and temperature T in the range of 298 K to 323 K is significantly improved, and the results of coefficient dD/dT is 75.33 kHz/K. Finally, this method promotes the average temperature measurement sensitivity (below 10 Hz) of our setup from 0.49 K/Hz1/2 to 0.22 K/Hz1/2.

quant-ph↗

arXiv2022

Microwave heating effect on diamond sample of NV centers

Diamond samples of defects with negative charged nitrogen-vacancy (NV) centers are promising solid state spin sensors suitable for quantum information processing, high sensitive measurements of magnetic, electric and thermal fields in nanoscale. The diamond defect with a NV center is unique for its robust temperature-dependent zero field splitting Dgs of the triplet ground state. This property enables optical readout of electron spin states through manipulation of the ground triplet state using microwave resonance with Dgs from 100 K to about 600 K. Thus, prohibiting Dgs from unwanted external thermal disturbances is crucial for an accurate measurement using diamond NV sensors. Our observation demonstrates the existence of a prominent microwave heating effect on the diamond samples of NV centers. The effect is inevitable to shift Dgs and cause measurement errors. The temperature increment caused by the effect monotonically depends on the power and the duration of microwave irradiation. The effect is obvious with the microwave irradiation in the continuous mode and some pulse sequence modes, but is neglectable for the quantum lock-in XY8-N method.

cond-mat.mes-hall↗

arXiv2019

Seesaw-Net: Convolution Neural Network With Uneven Group Convolution

In this paper, we are interested in boosting the representation capability of convolution neural networks which utilizing the inverted residual structure. Based on the success of Inverted Residual structure[Sandler et al. 2018] and Interleaved Low-Rank Group Convolutions[Sun et al. 2018], we rethink this two pattern of neural network structure, rather than NAS(Neural architecture search) method[Zoph and Le 2017; Pham et al. 2018; Liu et al. 2018b], we introduce uneven point-wise group convolution, which provide a novel search space for designing basic blocks to obtain better trade-off between representation capability and computational cost. Meanwhile, we propose two novel information flow patterns that will enable cross-group information flow for multiple group convolution layers with and without any channel permute/shuffle operation. Dense experiments on image classification task show that our proposed model, named Seesaw-Net, achieves state-of-the-art(SOTA) performance with limited computation and memory cost. Our code will be open-source and available together with pre-trained models.

cs.CV↗

arXiv2019

SeesawFaceNets: sparse and robust face verification model for mobile platform

Deep Convolutional Neural Network (DCNNs) come to be the most widely used solution for most computer vision related tasks, and one of the most important application scenes is face verification. Due to its high-accuracy performance, deep face verification models of which the inference stage occurs on cloud platform through internet plays the key role on most prectical scenes. However, two critical issues exist: First, individual privacy may not be well protected since they have to upload their personal photo and other private information to the online cloud backend. Secondly, either training or inference stage is time-comsuming and the latency may affect customer experience, especially when the internet link speed is not so stable or in remote areas where mobile reception is not so good, but also in cities where building and other construction may block mobile signals. Therefore, designing lightweight networks with low memory requirement and computational cost is one of the most practical solutions for face verification on mobile platform. In this paper, a novel mobile network named SeesawFaceNets, a simple but effective model, is proposed for productively deploying face recognition for mobile devices. Dense experimental results have shown that our proposed model SeesawFaceNets outperforms the baseline MobilefaceNets, with only {\bf66\%}(146M VS 221M MAdds) computational cost, smaller batch size and less training steps, and SeesawFaceNets achieve comparable performance with other SOTA model e.g. mobiface with only {\bf54.2\%}(1.3M VS 2.4M) parameters and {\bf31.6\%}(146M VS 462M MAdds) computational cost, It is also eventually competitive against large-scale deep-networks face recognition on all 5 listed public validation datasets, with {\bf6.5\%}(4.2M VS 65M) parameters and {\bf4.35\%}(526M VS 12G MAdds) computational cost.

cs.CV↗

arXiv2018

A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing

This paper presents a programmable in-memory-computing processor, demonstrated in a 65nm CMOS technology. For data-centric workloads, such as deep neural networks, data movement often dominates when implemented with today's computing architectures. This has motivated spatial architectures, where the arrangement of data-storage and compute hardware is distributed and explicitly aligned to the computation dataflow, most notably for matrix-vector multiplication. In-memory computing is a spatial architecture where processing elements correspond to dense bit cells, providing local storage and compute, typically employing analog operation. Though this raises the potential for high energy efficiency and throughput, analog operation has significantly limited robustness, scale, and programmability. This paper describes a 590kb in-memory-computing accelerator integrated in a programmable processor architecture, by exploiting recent approaches to charge-domain in-memory computing. The architecture takes the approach of tight coupling with an embedded CPU, through accelerator interfaces enabling integration in the standard processor memory space. Additionally, a near-memory-computing datapath both enables diverse computations locally, to address operations required across applications, and enables bit-precision scalability for matrix/input-vector elements, through a bit-parallel/bit-serial (BP/BS) scheme. Chip measurements show an energy efficiency of 152/297 1b-TOPS/W and throughput of 4.7/1.9 1b-TOPS (scaling linearly with the matrix/input-vector element precisions) at VDD of 1.2/0.85V. Neural network demonstrations with 1-b/4-b weights and activations for CIFAR-10 classification consume 5.3/105.2 $μ$J/image at 176/23 fps, with accuracy at the level of digital/software implementation (89.3/92.4 $\%$ accuracy).

cs.AR↗