arXiv subjects

Junji Tojo

Publications and source records attributed to Junji Tojo.

4 recordsLinked to original sources

arXiv2026

Hit-rate capability of a silicon strip detector module for decay positron detection in the J-PARC muon $g-2$/EDM experiment

In the J-PARC muon $g-2$/EDM experiment, a silicon strip detector will be used to detect positrons from muon decays. The detector consists of planes of detector modules arranged radially. The expected maximum hit rate reaches 1.4~MHz per sensor strip, and achieving high detection efficiency even under such hit-rate conditions is a key performance requirement. We have developed the smallest unit of the detector module, and its performance was evaluated using a muon beam at the J-PARC MLF H-line. The specifications of the detector module and the evaluated hit-rate capability are described in this article.

physics.ins-det↗

arXiv2024

The quality assurance test of the SliT ASIC for the J-PARC muon $g-2$/EDM experiment

The SliT ASIC is a readout chip for the silicon strip detector to be used at the J-PARC muon $g-2$/EDM experiment. The production version of SliT128D was designed and mass production was finished. A quality assurance test method for bare SliT128D chips was developed to provide a sufficient number of chips for the experiment. The quality assurance test of the SliT128D chips was performed and 5735 chips were inspected. No defect was observed in chips of 84.3%. Accepting a few channels with poor time walk performance out of 128 channels per chip, more than 90% yield can be achieved, which is sufficient to construct the whole detector.

physics.ins-det↗

arXiv2020

SliT: A Strip-sensor Readout Chip with Subnanosecond Time-walk for the J-PARC Muon $g-2$/EDM Experiment

A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and LVDS drivers. A distinct feature of the SliT is utilization of the zero-cross architecture, which consists of a CR-RC filter followed by a CR circuit as a voltage differentiator. This architecture enables to generate hit signals with subnanosecond amplitude-independent time walk, which is the primary requirement for the experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between 0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$ (rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other functionalities such as a strip-sensor readout chip have also been proven in the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM experiment.

physics.ins-det↗

arXiv2019

Prototype Front-end ASIC for Silicon-strip Detectors of J-PARC Muon g-2/EDM Experiment

We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to explore new physics beyond the Standard Model. Since the time and momentum of positrons from muon decay are key information in the experiment, a fast response with high granularity is demanded to silicon-strip detectors as the positron tracker. The readout ASIC is thus required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us with 5 ns time resolution. To satisfy the experimental requirements, an analog prototype ASIC was newly designed with the Silterra 180 nm CMOS technology. In the evaluation test, the time-walk was demonstrated to reach 0.8~ns with a sufficient dynamic range of 6~MIPs and pulse width of 45~ns for 1 MIP event. The design details and performance of the ASIC are discussed in this article.

physics.ins-det↗