arXiv subjects

Keren Bergman

Publications and source records attributed to Keren Bergman.

16 recordsLinked to original sources

arXiv2025

Highly Uniform Thermally Undercut Silicon Photonic Devices in a 300 mm CMOS Foundry Process

Silicon photonic devices fundamental to high-density wavelength-division multiplexed (DWDM) optical links and photonic switching networks, such as resonant modulators and Mach-Zehnder interferometers (MZIs), are highly sensitive to fabrication variations and operational temperature swings. However, thermal tuning to compensate for fabrication and operational temperature variations can result in prohibitive power consumption, challenging the scalability of energy-efficient photonic integrated circuits (PICs). In this work, we develop and demonstrate a wafer-scale thermal undercut process in a 300 mm complementary metal oxide semiconductor (CMOS) foundry that dramatically improves the thermal isolation of thermo-optic devices by selectively removing substrate material beneath the waveguides and resonators. This approach significantly reduces the power required for thermal tuning across multiple device architectures, achieving almost a 5$\times$ improvement in tuning efficiency in a state-of-the-art 4.5 $μ$m radius microdisk modulator and a 40$\times$ improvement in efficiency for a MZI phase shifter. To the best of the authors' knowledge, we demonstrate the first wafer-scale comparison of non-undercut and undercut silicon photonic devices using comprehensive wafer-scale measurements across 64 reticles of a 300 mm silicon-on-insulator (SOI) wafer. Further, we demonstrate a comprehensive wafer-scale analysis of the influence of undercut trench opening geometry on device tuning efficiency. Notably, we observe highly uniform performance across the full 300 mm wafer for multiple device types, emphasizing that our process can be scaled to large-scale photonic circuits with high yield. These results open new opportunities for large-scale integrated photonic circuits using thermo-optic devices, paving the way for scalable, low-power silicon photonic systems.

physics.optics↗

arXiv2025

Tri-layer SiN-on-Si 8x8 Optical Switches with Thermo-optic and Electro-optic Actuators

We present two spatial-multiplexed switch-and-select (S&S) 8x8 optical switches incorporating a tri-layer SiN-on-Si platform, one equipped with thermo-optic (T-O) and the other electro-optic (E-O) switching elements. To the best of our knowledge, the electro-optic switch fabric is the first-of-its-kind device assembled in such a multi-layer platform. The shuffle between the multiplexer and demultiplexer array is established via a tri-layer Si-SiN-SiN structure, creating a three-dimensional crossing-free photonic shuffle network. At the same time, the implementation of the S&S topology can effectively suppress the first-order crosstalk. The measured on-chip losses for the T-O switch range from 2.1 to 11.5 dB, with a 5.2 dB average, while the E-O device exhibits losses between 8.7 to 19.6 dB, with a 15.1 dB average. Both switches demonstrate ultra-low crosstalk, with measured ranges of 38.9 to 50.8 dB and 42.8 to 51.9 dB, for the T-O and E-O devices respectively. The switching times are 17.6 us for the T-O switch and 5.9 ns with the E-O actuated one. These performance metrics highlight the potential of these switches for next-generation data center applications.

physics.optics↗

arXiv2023

3D photonics for ultra-low energy, high bandwidth-density chip data links

Artificial intelligence (AI) hardware is positioned to unlock revolutionary computational abilities across diverse fields ranging from fundamental science [1] to medicine [2] and environmental science [3] by leveraging advanced semiconductor chips interconnected in vast distributed networks. However, AI chip development has far outpaced that of the networks that connect them, as chip computation speeds have accelerated a thousandfold faster than communication bandwidth over the last two decades [4, 5]. This gap is the largest barrier for scaling AI performance [6, 7] and results from the disproportionately high energy expended to transmit data [8], which is two orders of magnitude more intensive than computing [9]. Here, we show a leveling of this long-standing discrepancy and achieve the lowest energy optical data link to date through dense 3D integration of photonic and electronic chips. At 120 fJ of consumed energy per communicated bit and 5.3 Tb/s bandwidth per square millimeter of chip area, our platform simultaneously achieves a twofold improvement in both energy consumption and bandwidth density relative to prior demonstrations [10, 11]. These improvements are realized through employing massively parallel 80 channel microresonator-based transmitter and receiver arrays operating at 10 Gb/s per channel, occupying a combined chip footprint of only 0.32 mm2. Furthermore, commercial complementary metal-oxide-semiconductor (CMOS) foundries fabricate both the electronic and photonic chips on 300 mm wafers, providing a clear avenue to volume scaling. Through these demonstrated ultra-energy efficient, high bandwidth data communication links, this work eliminates the bandwidth bottleneck between spatially distanced compute nodes and will enable a fundamentally new scale of future AI computing hardware without constraints on data locality.

physics.optics↗

arXiv2023

Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics

The diversity of workload requirements and increasing hardware heterogeneity in emerging high performance computing (HPC) systems motivate resource disaggregation. Resource disaggregation allows compute and memory resources to be allocated individually as required to each workload. However, it is unclear how to efficiently realize this capability and cost-effectively meet the stringent bandwidth and latency requirements of HPC applications. To that end, we describe how modern photonics can be co-designed with modern HPC racks to implement flexible intra-rack resource disaggregation and fully meet the bit error rate (BER) and high escape bandwidth of all chip types in modern HPC racks. Our photonic-based disaggregated rack provides an average application speedup of 11% (46% maximum) for 25 CPU and 61% for 24 GPU benchmarks compared to a similar system that instead uses modern electronic switches for disaggregation. Using observed resource usage from a production system, we estimate that an iso-performance intra-rack disaggregated HPC system using photonics would require 4x fewer memory modules and 2x fewer NICs than a non-disaggregated baseline.

cs.DC↗

arXiv2023

Process Variation-Aware Compact Model of Strip Waveguides for Photonic Circuit Simulation

We report a novel process variation-aware compact model of strip waveguides that is suitable for circuit-level simulation of waveguide-based process design kit (PDK) elements. The model is shown to describe both loss and -- using a novel expression for the thermo-optic effect in high index contrast materials -- the thermo-optic behavior of strip waveguides. A novel group extraction method enables modeling the effective index's ($n_{\mathrm{eff}}$) sensitivity to local process variations without the presumption of variation source. Use of Euler-bend Mach-Zehnder interferometers (MZIs) fabricated in a 300~mm wafer run allow model parameter extraction at widths up to 2.5~$μ$m (highly multi-mode) with strong suppression of higher-order mode excitation. Experimental results prove the reported model can self-consistently describe waveguide phase, loss, and thermo-optic behavior across all measured devices over an unprecedented range of optical bandwidth, waveguide widths, and temperatures.

physics.optics↗

arXiv2022

Massively Scalable Wavelength Diverse Integrated Photonic Linear Neuron

As computing resource demands continue to escalate in the face of big data, cloud-connectivity and the internet of things, it has become imperative to develop new low-power, scalable architectures. Neuromorphic photonics, or photonic neural networks, have become a feasible solution for the physical implementation of efficient algorithms directly on-chip. This application is primarily due to the linear nature of light and the scalability of silicon photonics, specifically leveraging the wide-scale complementary metal-oxide-semiconductor (CMOS) manufacturing infrastructure used to fabricate microelectronics chips. Current neuromorphic photonic implementations stem from two paradigms: wavelength coherent and incoherent. Here, we introduce a novel architecture that supports coherent and incoherent operation to increase the capability and capacity of photonic neural networks with a dramatic reduction in footprint compared to previous demonstrations. As a proof-of-principle, we experimentally demonstrate simple addition and subtraction operations on a foundry-fabricated silicon photonic chip. Additionally, we experimentally validate an on-chip network to predict the logical 2-bit gates AND, OR, and XOR to accuracies of $96.8\%, 99\%,$ and $98.5\%$, respectively. This architecture is compatible with highly wavelength parallel sources, enabling massively scalable photonic neural networks.

cs.ET↗

arXiv2022

Fabrication-Robust Silicon Photonic Devices in Standard Sub-Micron Silicon-on-Insulator Processes

Perturbations to the effective refractive index from nanometer-scale fabrication variations in waveguide geometry plague high index-contrast photonic platforms including the ubiquitous sub-micron silicon-on-insulator (SOI) process. Such variations are particularly troublesome for phase-sensitive devices such as interferometers and resonators, which exhibit drastic changes in performance as a result of these fabrication-induced phase errors. In this Letter, we propose and experimentally demonstrate a design methodology for dramatically reducing device sensitivity to silicon width variations. We apply this methodology to a highly phase-sensitive device, the ring-assisted Mach Zehnder interferometer (RAMZI), and show comparable performance and footprint to state-of-the-art devices while substantially reducing stochastic phase errors from etch variations. This decrease in sensitivity is directly realized as energy savings by significantly lowering the required corrective thermal tuning power, providing a promising path towards ultra-energy-efficient large-scale silicon photonic circuits.

physics.optics↗

arXiv2021

Integrated Kerr frequency comb-driven silicon photonic transmitter

The exponential growth of computing needs for artificial intelligence and machine learning has had a dramatic impact on data centre energy consumption, which has risen to environmentally significant levels. Using light to send information between compute nodes can dramatically decrease this energy consumption while simultaneously increasing bandwidth. Through wavelength-division multiplexing with chip-based microresonator Kerr frequency combs, independent information channels can be encoded onto many distinct colours of light in the same optical fibre for massively parallel data transmission with low energy. While previous demonstrations have relied on benchtop equipment for filtering and modulating Kerr comb wavelength channels, data centre interconnects require a compact on-chip form factor for these operations. Here, we demonstrate the first integrated silicon photonic transmitter using a Kerr comb source. The demonstrated architecture is scalable to hundreds of wavelength channels, enabling a fundamentally new class of massively parallel terabit-scale optical interconnects for future green hyperscale data centres.

physics.app-ph↗

arXiv2020

COUDER: Robust Topology Engineering for Optical Circuit Switched Data Center Networks

Many optical circuit switched data center networks (DCN) have been proposed in the past to attain higher capacity and topology reconfigurability, though commercial adoption of these architectures have been minimal. One major challenge these architectures face is the difficulty of handling uncertain traffic demands using commercial optical circuit switches (OCS) with high switching latency. Prior works have generally focused on developing fast-switching OCS prototypes to quickly react to traffic changes through frequent reconfigurations. This approach, however, adds tremendous complexity to the control plane, and raises the barrier for commercial adoption of optical circuit switched data center networks. We propose COUDER, a robust topology and routing optimization framework for reconfigurable optical circuit switched data centers. COUDER optimizes topology and routing based on a convex set of traffic matrices, and offers strict throughput guarantees for any future traffic matrices bounded by the convex set. For the bursty traffic demands that are unbounded by the convex set, we employ a desensitization technique to reduce performance hit. This enables COUDER to generate topology and routing solutions capable of handling unexpected traffic changes without relying on frequent topology reconfigurations. Our extensive evaluations based on Facebook's production DCN traces show that, even with daily reconfiguration, COUDER achieves about 20\% higher throughput, and about 32\% lower average hop count compared to cost-equivalent static topologies. Our work shows that adoption of reconfigurable topologies in commercial DCNs is feasible even without fast OCSs.

cs.NI↗

arXiv2020

Optically Connected Memory for Disaggregated Data Centers

Recent advances in integrated photonics enable the implementation of reconfigurable, high-bandwidth, and low energy-per-bit interconnects in next-generation data centers. We propose and evaluate an Optically Connected Memory (OCM) architecture that disaggregates the main memory from the computation nodes in data centers. OCM is based on micro-ring resonators (MRRs), and it does not require any modification to the DRAM memory modules. We calculate energy consumption from real photonic devices and integrate them into a system simulator to evaluate performance. Our results show that (1) OCM is capable of interconnecting four DDR4 memory channels to a computing node using two fibers with 1.07 pJ energy-per-bit consumption and (2) OCM performs up to 5.5x faster than a disaggregated memory with 40G PCIe NIC connectors to computing nodes.

cs.AR↗

arXiv2020

METTEOR: Robust Multi-Traffic Topology Engineering for Commercial Data Center Networks

Numerous optical circuit switched data center networks have been proposed over the past decade for higher capacity, though commercial adoption of these architectures have been minimal so far. One major challenge commonly facing these architectures is the difficulty of handling bursty traffic with optical circuit switches (OCS) with high switching latency. Prior works generally rely on fast-switching OCS prototypes to better react to traffic changes via frequent reconfigurations. This approach, unfortunately, adds further complexity to the control plane. We propose METTEOR, an easily deployable solution for optical circuit switched data centers, that is designed for the current capabilities of commercial OCSs. Using multiple predicted traffic matrices, METTEOR designs data center topologies that are less sensitive to traffic changes, thus eliminating the need of frequently reconfiguring OCSs upon traffic changes. Results based on extensive evaluations using production traces show that METTEOR increases the percentage of direct-hop traffic by about 80% over a fat tree at comparable cost, and by about 30% over a uniform mesh, at comparable maximum link utilizations. Compared to ideal solutions that reconfigure OCSs on every traffic matrix, METTEOR achieves close-to-optimal bandwidth utilization even with biweekly reconfiguration. This drastically lowers the controller and management complexity needed to perform METTEOR in commercial settings.

cs.NI↗

arXiv2017

Software-Defined Silicon Photonics based Metro Node for Spatial and Wavelength Superchannel Switching

Due to the growing popularity of optical superchannels and software defined networking, reconfigurable optical add-drop multiplexer (ROADM) architectures for superchannel switching have recently attracted significant attention. ROADMs based on micro electro-mechanical system (MEMS) and liquid crystal-on-silicon (LCoS) technologies are predominantly used. Motivated by requirements for low power, high-speed, small area footprint and compact switching solutions, we propose and demonstrate spatial and wavelength flexible superchannel switching using monolithically integrated silicon photonics (SiP) micro-ring resonators (MRR). We demonstrate the MRRs capabilities and potential to be used as a fundamental building block in ROADMs. Unicast and multicast switching operation of an entire superchannel is demonstrated after transmission over 50 km of standard single mode fiber. The performance of each sub-channel from the 120 Gb/s QPSK Nyquist superchannel is analyzed and degradation in error vector magnitude performance was observed for outer sub-channels due to the 3-dB bandwidth of the MRRs, which is comparable with the superchannel bandwidth. However, all sub-channels for all switching cases (unicast, multicast and bi-directional operation) exhibit performance far below the 7% FEC limit. The switching time of the SiP MRR chip is such that high capacity superchannel interconnects between users can be setup and reconfigured on the microsecond timescale.

cs.NI↗

arXiv2015

A highly scalable fully non-blocking silicon photonic switch fabric

Large port count spatial optical switches will facilitate flexible and energy efficient data movement in future data communications systems, especially if they are capable of nanosecond-order reconfiguration times. In this work, we demonstrate an 8x8 microring-based silicon photonic switch with software controlled switching. The proposed switch architecture is modular as it assembles multiple identical components with multiplexing/demultiplexing functionalities. The switch is fully non-blocking, has path independent insertion loss, low crosstalk and is straightforward to control. A scalability analysis shows that this architecture can scale to very large port counts. This work represents the first demonstration of real-time firmware controlled switching with silicon photonics devices integrated at the chip scale.

physics.optics↗

arXiv2015

Integrated switch for simultaneous mode-division multiplexing (MDM) and wavelength-division multiplexing (WDM)

Leveraging the spatial modes of multimode waveguides using mode-division multiplexing (MDM) on an integrated photonic chip allows unprecedented scaling of bandwidth density for on-chip communication. Switching channels between waveguides is critical for future scalable optical networks, but its implementation in multimode waveguides must address how to simultaneously control modes with vastly different optical properties. Here we present a platform for switching signals between multimode waveguides based on individually processing the spatial mode channels using single-mode elements. Using this wavelength-division multiplexing (WDM) compatible platform, we demonstrate a 1x2 multimode switch for a silicon chip which routes four data channels with low (<-20 dB) crosstalk. We show bit-error rates below 10^-9 and power penalties below 1.4 dB on all channels while routing 10 Gbps data when each channel is input and routed separately. The switch exhibits an additional power penalty of less than 2.4 dB when all four channels are simultaneously routed.

physics.optics↗

arXiv2014

Extrinsic Photodiodes for Integrated Mid-Infrared Silicon Photonics

Silicon photonics has recently been proposed for a diverse set of applications at mid-infrared wavelengths, the implementation of which require on-chip photodetectors. In planar geometries, dopant-based extrinsic photoconductors have long been used for mid-infrared detection with Si and Ge acting as host materials. Leveraging the dopant-induced sub-bandgap trap-states used in bulk photoconductors for waveguide integrated mid-infrared detectors offers simple processing, integration, and operation throughout the mid-infrared by appropriate choice of dopant. In particular, Si doped with Zn forms two trap levels ~ 0.3 eV and ~ 0.58 eV above the valence band, and has been utilized extensively for cryogenically cooled bulk extrinsic photoconductors. In this letter, we present room temperature operation of Zn+ implanted Si waveguide photodiodes from 2200 nm to 2400 nm, with measured responsivities of up to 87 mA/W and low dark currents of < 10 microamps.

physics.optics↗

arXiv2013

Simultaneous Mode and Wavelength Division Multiplexing On-Chip

Significant effort in optical-fiber research has been put in recent years into realizing mode-division multiplexing (MDM) in conjunction with wavelength-division multiplexing (WDM) to enable further scaling of the communication bandwidth per fiber. In contrast almost all integrated photonics operate exclusively in the single-mode regime. MDM is rarely considered for integrated photonics due to the difficulty in coupling selectively to high-order modes which usually results in high inter-modal crosstalk. Here we show the first demonstration of simultaneous on-chip mode and wavelength division multiplexing with low modal crosstalk and loss. Our approach can potentially increase the aggregate data rate by many times for on-chip ultra-high bandwidth communications.

physics.optics↗