Highly Uniform Thermally Undercut Silicon Photonic Devices in a 300 mm CMOS Foundry Process

Abstract

Silicon photonic devices fundamental to high-density wavelength-division multiplexed (DWDM) optical links and photonic switching networks, such as resonant modulators and Mach-Zehnder interferometers (MZIs), are highly sensitive to fabrication variations and operational temperature swings. However, thermal tuning to compensate for fabrication and operational temperature variations can result in prohibitive power consumption, challenging the scalability of energy-efficient photonic integrated circuits (PICs). In this work, we develop and demonstrate a wafer-scale thermal undercut process in a 300 mm complementary metal oxide semiconductor (CMOS) foundry that dramatically improves the thermal isolation of thermo-optic devices by selectively removing substrate material beneath the waveguides and resonators. This approach significantly reduces the power required for thermal tuning across multiple device architectures, achieving almost a 5$\times$ improvement in tuning efficiency in a state-of-the-art 4.5 $\mu$m radius microdisk modulator and a 40$\times$ improvement in efficiency for a MZI phase shifter. To the best of the authors' knowledge, we demonstrate the first wafer-scale comparison of non-undercut and undercut silicon photonic devices using comprehensive wafer-scale measurements across 64 reticles of a 300 mm silicon-on-insulator (SOI) wafer. Further, we demonstrate a comprehensive wafer-scale analysis of the influence of undercut trench opening geometry on device tuning efficiency. Notably, we observe highly uniform performance across the full 300 mm wafer for multiple device types, emphasizing that our process can be scaled to large-scale photonic circuits with high yield. These results open new opportunities for large-scale integrated photonic circuits using thermo-optic devices, paving the way for scalable, low-power silicon photonic systems.