arXiv subjects

Kwunhang Wong

Publications and source records attributed to Kwunhang Wong.

8 recordsLinked to original sources

arXiv2026

Potentials and Limitations on Different Busbar Protections in Industrial Applications

Busbar protection is a cornerstone of industrial power system reliability, as failures at switchgear can propagate rapidly and extend restoration times. The Taiwan "303 blackout" in 2022, initiated by a short-circuit fault and aggravated by CT supervision lockout, illustrates the severe consequences of inadequate designs on busbar protection in centralized grids. Despite extensive academic and industrial guidance, practical challenges remain in busbar protection design, including CT placement, dynamic zone selection, CT saturation, and evolving fault scenarios. Standards and guides often fail to reflect operational limitations under diverse system conditions. This paper provides a structured evaluation of busbar protection (BBP) schemes in industrial applications. Leakage-to-frame, high-impedance differential (87Z), interlocking overcurrent (ILOC), electronic (EBBP), and numerical (NBBP) schemes are examined with respect to their operating principles, implementation requirements, and suitability for different bus configurations. Comparative analysis highlights clear trade-offs in different busbar protection schemes. The main contributions are: (i) systematic review of classical and modern busbar protection schemes, (ii) identification of operational limitations with various busbar protection, and (iii) comparison on the integration of CT supervision, check zones, and directional checks in NBBP to mitigate maloperations. The discussion reinforces the role of robust busbar protection design in preventing cascading outages and maintaining system reliability.

eess.SY↗

arXiv2026

Comparative Analysis on Inertia Estimation Algorithms (IEAs) in Providing Proper Frequency Response

The inertia constant H[s] is a fundamental indicator of power system resilience, linking power imbalance between generation and load to frequency deviation. It is essential in frequency reserve dispatch under stability-constrained optimal power flow (OPF), demand response (DR) in ancillary service, system decoupling and frequency control in modern power system. While the inertia constant is traditionally defined as the intrinsic kinetic energy of synchronous generators on bar normalized to the power base, this neglects the releasable power under nonlinear dynamics and control inside HVDC and Inverter-based Resources (IBRs). Accurate real-time inertia estimation is therefore essential to perform proper frequency control and to indicate the risks of failure in frequency restoration. It, however, is challenging with noisy frequency measurement under event-driven parameter jumps and locational transient responses. This paper presents a systematic comparative analysis on inertia estimation algorithms (IEAs) for frequency response applications. Classical methods such as filtering and fitting under measurement-based methods are benchmarked against data-based parameter estimation techniques such as recursive least squares (RLS) and model-based methods such as Kalman filtering (KF). The main contributions are: (i) a holistic review of model- and data-based inertia estimation methods, (ii) exploration on the effect of IEA to wind-based inertia emulation strategies. The findings underscore the need for robust, adaptive, and data-driven estimation frameworks to ensure secure operation of future low-inertia grids.

eess.SY↗

arXiv2026

RRAM-DP: Device-Calibrated Differential Privacy for In-Memory Edge Learning

Edge Artificial Intelligence of Things (AIoT) systems often collect sensitive data in situ, raising serious privacy concerns. Resistive-switching random-access memory (RRAM) is an attractive substrate for efficient AIoT thanks to its multi-bit storage and compute-in-memory (CiM) capabilities, while its inherently stochastic write behavior provides a natural source of randomness that can be leveraged for differential privacy (DP) protection. Yet how to transform this device-level randomness-typically viewed as detrimental to accuracy-into a principled randomized mechanism while preserving model utility remains underexplored. We propose RRAM-DP, a hardware-algorithm co-design that relaxes RRAM write-verify operations to inject calibrated noise for inherently (epsilon, delta)-DP with formal DP analysis; together with pretraining techniques, it renders a novel private, high-utility CiM training paradigm. On CIFAR-10/100, STS-B, and SST-2, RRAM-DP-SGD incurs at best only a 3.8% accuracy drop at (epsilon=2, delta=O(1/n))-DP relative to non-private SGD. At the same privacy level, RRAM-DP-SGD delivers up to 57x and 3.2x energy savings and 2.7x and 1.8x speedups over A100 and DiVa-GEMM, respectively. These results point toward efficient, privacy-preserving in-memory training on RRAM at the edge.

cs.CR↗

arXiv2026

Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design

The rapid deployment of deep neural network (DNN) accelerators in safety-critical domains such as autonomous vehicles, healthcare systems, and financial infrastructure necessitates robust mechanisms to safeguard data confidentiality and computational integrity. Existing security solutions for DNN accelerators, however, suffer from excessive hardware resource demands and frequent off-chip memory access overheads, which degrade performance and scalability. To address these challenges, this paper presents a secure and efficient memory protection framework for DNN accelerators with minimal overhead. First, we propose a bandwidth-aware cryptographic scheme that adapts encryption granularity based on memory traffic patterns, striking a balance between security and resource efficiency. Second, we observe that both the overlapping regions in the intra-layer tiling's sliding window pattern and those resulting from inter-layer tiling strategy discrepancies introduce substantial redundant memory accesses and repeated computational overhead in cryptography. Third, we introduce a multi-level authentication mechanism that effectively eliminates unnecessary off-chip memory accesses, enhancing performance and energy efficiency. Experimental results show that this work decreases performance overhead by over 12% and achieves 87% energy efficiency improvement for both server and edge neural processing units (NPUs), while ensuring robust scalability.

cs.CR↗

arXiv2025

When Pipelined In-Memory Accelerators Meet Spiking Direct Feedback Alignment: A Co-Design for Neuromorphic Edge Computing

Spiking Neural Networks (SNNs) are increasingly favored for deployment on resource-constrained edge devices due to their energy-efficient and event-driven processing capabilities. However, training SNNs remains challenging because of the computational intensity of traditional backpropagation algorithms adapted for spike-based systems. In this paper, we propose a novel software-hardware co-design that introduces a hardware-friendly training algorithm, Spiking Direct Feedback Alignment (SDFA) and implement it on a Resistive Random Access Memory (RRAM)-based In-Memory Computing (IMC) architecture, referred to as PipeSDFA, to accelerate SNN training. Software-wise, the computational complexity of SNN training is reduced by the SDFA through the elimination of sequential error propagation. Hardware-wise, a three-level pipelined dataflow is designed based on IMC architecture to parallelize the training process. Experimental results demonstrate that the PipeSDFA training accelerator incurs less than 2% accuracy loss on five datasets compared to baselines, while achieving 1.1X~10.5X and 1.37X~2.1X reductions in training time and energy consumption, respectively compared to PipeLayer.

cs.AR↗

arXiv2025

Resistive memory-based zero-shot liquid state machine for multimodal event data learning

The human brain is a complex spiking neural network (SNN), capable of learning multimodal signals in a zero-shot manner by generalizing existing knowledge. Remarkably, it maintains minimal power consumption through event-based signal propagation. However, replicating the human brain in neuromorphic hardware presents both hardware and software challenges. Hardware limitations, such as the slowdown of Moore's law and Von Neumann bottleneck, hinder the efficiency of digital computers. Additionally, SNNs are characterized by their software training complexities. To this end, we propose a hardware-software co-design on a 40 nm 256 Kb in-memory computing macro that physically integrates a fixed and random liquid state machine (LSM) SNN encoder with trainable artificial neural network (ANN) projections. We showcase the zero-shot LSM-based learning of multimodal events on the N-MNIST and N-TIDIGITS datasets, including visual and audio data association, as well as neural and visual data alignment for brain-machine interfaces. Our co-design achieves classification accuracy comparable to fully optimized software models, resulting in a 152.83 and 393.07-fold reduction in training costs compared to SOTA contrastive language-image pre-training (CLIP) and Prototypical networks, and a 23.34 and 160-fold improvement in energy efficiency compared to cutting-edge digital hardware, respectively. These proof-of-principle prototypes demonstrate zero-shot multimodal events learning capability for emerging efficient and compact neuromorphic hardware.

cs.ET↗

arXiv2024

SNNGX: Securing Spiking Neural Networks with Genetic XOR Encryption on RRAM-based Neuromorphic Accelerator

Biologically plausible Spiking Neural Networks (SNNs), characterized by spike sparsity, are growing tremendous attention over intellectual edge devices and critical bio-medical applications as compared to artificial neural networks (ANNs). However, there is a considerable risk from malicious attempts to extract white-box information (i.e., weights) from SNNs, as attackers could exploit well-trained SNNs for profit and white-box adversarial concerns. There is a dire need for intellectual property (IP) protective measures. In this paper, we present a novel secure software-hardware co-designed RRAM-based neuromorphic accelerator for protecting the IP of SNNs. Software-wise, we design a tailored genetic algorithm with classic XOR encryption to target the least number of weights that need encryption. From a hardware perspective, we develop a low-energy decryption module, meticulously designed to provide zero decryption latency. Extensive results from various datasets, including NMNIST, DVSGesture, EEGMMIDB, Braille Letter, and SHD, demonstrate that our proposed method effectively secures SNNs by encrypting a minimal fraction of stealthy weights, only 0.00005% to 0.016% weight bits. Additionally, it achieves a substantial reduction in energy consumption, ranging from x59 to x6780, and significantly lowers decryption latency, ranging from x175 to x4250. Moreover, our method requires as little as one sample per class in dataset for encryption and addresses hessian/gradient-based search insensitive problems. This strategy offers a highly efficient and flexible solution for securing SNNs in diverse applications.

cs.CR↗

arXiv2024

Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of Deep Neural Networks

Deep neural networks (DNNs), such as the widely-used GPT-3 with billions of parameters, are often kept secret due to high training costs and privacy concerns surrounding the data used to train them. Previous approaches to securing DNNs typically require expensive circuit redesign, resulting in additional overheads such as increased area, energy consumption, and latency. To address these issues, we propose a novel hardware-software co-design approach for DNN intellectual property (IP) protection that capitalizes on the inherent aging characteristics of circuits and a novel differential orientation fine-tuning (DOFT) to ensure effective protection. Hardware-wise, we employ random aging to produce authorized chips. This process circumvents the need for chip redesign, thereby eliminating any additional hardware overhead during the inference procedure of DNNs. Moreover, the authorized chips demonstrate a considerable disparity in DNN inference performance when compared to unauthorized chips. Software-wise, we propose a novel DOFT, which allows pre-trained DNNs to maintain their original accuracy on authorized chips with minimal fine-tuning, while the model's performance on unauthorized chips is reduced to random guessing. Extensive experiments on various models, including MLP, VGG, ResNet, Mixer, and SwinTransformer, with lightweight binary and practical multi-bit weights demonstrate that the proposed method achieves effective IP protection, with only 10\% accuracy on unauthorized chips, while preserving nearly the original accuracy on authorized ones.

cs.CR↗