arXiv subjects

Lars R. Schreiber

Publications and source records attributed to Lars R. Schreiber.

At least 19 recordsLinked to original sources

arXiv2026

Valley-Enabled Intrinsic Dresselhaus Spin-Orbit Coupling in Silicon

We develop a symmetry-based theory of spin-orbit-valley coupling in silicon that reveals an intrinsic source of Dresselhaus spin-orbit coupling independent of interfaces or external electric fields. Treating the valley degree of freedom as a symmetry-carrying quantum degree of freedom, we show that the Dresselhaus interaction is necessarily valley off-diagonal and that a bulk contribution proportional to the valley Pauli matrix $τ_1$ is symmetry allowed. Tight-binding calculations yield a bulk coupling more than an order of magnitude larger than typical interface-induced spin-orbit coupling; achieving the same energy scale through the interface-induced mechanism would require electric fields roughly 50 times larger than typical fields. We further derive the symmetry-allowed spin-valley couplings generated by magnetic-field gradients and show how they account for the valley-dependent Zeeman splitting observed in micromagnet experiments. A slight tilt of the background magnetic field out of the plane produces an additional isotropic contribution linear in $B_z$, providing an experimentally accessible signature of the corresponding coupling constant. Finally, we predict a spin-independent micromagnet-induced valley splitting in the $τ_3$ channel, which is distinct from the $τ_{1,2}$ channels generated by alloy disorder and therefore remains robust against disorder-induced cancellation. These results establish valley symmetry as a fundamental ingredient in the spin-orbit physics of silicon and provide new mechanisms for controlling and probing spin and valley degrees of freedom in silicon quantum devices.

cond-mat.mtrl-sci↗

arXiv2026

Enhanced intrinsic spin-orbit driving of a Loss-DiVincenzo qubit near the spin-valley hotspot in Si/SiGe

In most Si/SiGe-based spin qubit implementations, high-fidelity single-qubit gates are achieved using micromagnets, which enable the use of electric spin dipole resonance via synthetic spin-orbit coupling (s-SOC). In contrast, intrinsic spin-orbit coupling (i-SOC) in silicon is generally considered to be weak. However, in Si/SiGe heterostructures, theory predicts a substantial enhancement when the Zeeman splitting approaches the valley splitting if symmetry is reduced by an imperfect interface. Here, we demonstrate a Si/SiGe Loss-DiVincenzo qubit driven by i-SOC close to this so-called spin-valley hotspot. In particular, we characterize the Rabi frequency as a function of the energy detuning from the hotspot by sweeping both the magnetic field and quantum dot position. We observe the predicted enhancement of the Rabi frequency near the hotspot, but also find an asymmetry that deviates from existing theoretical models as well as distortions of the Chevron patterns near the hotspot. While we achieve an average single-qubit Clifford fidelity of 98.6 %, the strong variability of the valley splitting may impede the use of i-SOC-based control as a scalable operational strategy; understanding its effect is nevertheless important for reproducible high-fidelity control. Our results provide an empirical basis for refining current theoretical models of spin-valley physics in Si/SiGe heterostructures.

cond-mat.mes-hall↗

arXiv2026

Optimization of Si/SiGe Heterostructures for Large and Robust Valley Splitting in Silicon Qubits

Small and device-dependent valley splittings remain a key challenge for electron spin qubits in silicon (Si), directly limiting qubit fidelity, device uniformity, and the scalability of Si-based quantum processors. In silicon-germanium (SiGe) heterostructures, this problem can be addressed through engineering of the epitaxial layer stack. Several heuristic strategies have been proposed to enhance the energy gap between the two nearly degenerate valley states in strained Si/SiGe quantum wells (QWs), e.g., sharp Si/SiGe interfaces, Ge spikes, or oscillating Ge concentrations within the QW. Here, we develop a systematic variational optimization approach to compute optimal Ge concentration profiles that enhance selected properties of the intervalley coupling matrix element. Our free-shape optimization framework is augmented by realistic technological constraints to ensure feasibility of the resulting epitaxial profiles and is based on an effective-mass envelope-function theory accounting for strain and compositional alloy disorder. Previously proposed heterostructure designs are recovered as special cases of the constrained optimization problem. Our main result is a novel heterostructure design, which we refer to as the "modulated wiggle well", providing both a large deterministic enhancement of the valley splitting and a strong suppression of disorder-induced variability. In addition, this design enables wide electrical tunability of the valley splitting - from approximately $200\,μ\text{eV}$ to above $1\,\text{meV}$ - offering new opportunities for engineering robust and switchable silicon qubits.

cond-mat.mes-hall↗

arXiv2026

Mapping g-factors and complex intervalley coupling in Si/SiGe by conveyor-mode shuttling

As silicon spin qubit chips are increasing in qubit number and area, methods for the screening of qubit related material parameters become vital. Here we demonstrate the two-dimensional mapping of small variations of the electron g-factor of quantum dots formed in planar Si/SiGe quantum wells with precision better than $10^{-3}$ and with nanometer lateral resolution. We scan the electron g-factor across a 40 nm $\times$ 400 nm area and observe two g-factors per QD site which obey a striking symmetry and bimodal distribution across the area. These two g-factors relate to valley states of the electron in the quantum dot in agreement with a recent theoretical model. Using conveyor-belt shuttling of entangled electron spin pairs, complementary to the mapping of the local valley-splitting, we map the g-factor. We compare g-factor and valley splitting maps measured on the same device, and extract the complex intervalley coupling parameter along the shuttle trajectories applying a theoretical model of g-factor dependence on intervalley coupling. These maps will allow unprecedented insights into the spin-valley dynamics during qubit manipulation, readout and shuttling and serve as a benchmark for the engineering of Si/SiGe heterostructures for large-scale quantum chips.

quant-ph↗

arXiv2026

Impact of the local valley splitting on the coherence of conveyor-belt spin shuttling in $^{28}$Si/SiGe

Silicon quantum chips offer a promising path toward scalable, fault-tolerant quantum computing, with the potential to host millions of qubits. However, scaling up dense quantum-dot arrays and enabling qubit interconnections through shuttling are hindered by uncontrolled lateral variations of the valley splitting energy $E_{VS}$. We map $E_{VS}$ across a $40 \, $nm x $400 \, $nm region of a $^{28}$Si/Si$_{0.7}$Ge$_{0.3}$ shuttle device and analyze the spin coherence of a single electron spin transported by conveyor-belt shuttling. We observe that the $E_{VS}$ varies over a wide range from $1.5 \, μ$eV to $200 \, μ$eV and is dominated by SiGe alloy disorder. In regions of low $E_{VS}$ and at spin-valley resonances, spin coherence is reduced and its dependence on shuttle velocity matches predictions. Rapid and frequent traversal of low-$E_{VS}$ regions induces a regime of enhanced spin coherence explained by motional narrowing. By selecting shuttle trajectories that avoid problematic areas on the $E_{VS}$ map, we achieve transport over tens of microns with coherence limited only by the coupling to a static electron spin entangled with the mobile qubit. Our results provide experimental confirmation of the theory of spin-decoherence of mobile electron spin-qubits and present practical strategies to integrate conveyor-mode qubit shuttling into silicon quantum chips.

quant-ph↗

arXiv2026

Sharp periodic Ge concentration modulations beyond the conduction band valley wavevector $k_0$ in nuclear spin-free Si quantum wells

Periodic Ge modulations within strained Si quantum wells in SiGe heterostructures offer a route to deterministically enhance conduction-band valley splitting in Si, a key requirement for scalable spin-qubit quantum computing. Efficient enhancement requires modulations in the order of the Si valley wavevector $k_0$ (9.7 nm$^{-1}$), corresponding to a period of 0.64 nm and near-monolayer growth control. Using nuclear-spin-free molecular beam epitaxy with $^{28}$Si and $^{72}$Ge, we demonstrate Ge-modulated Si quantum wells with periods from 2.00 to 0.49 nm, including modulations at $k_0$ and $2k_0/3$. Synchrotron X-ray techniques and scanning transmission electron microscopy reveal laterally homogeneous Ge modulations over micrometer scales, with amplitudes up to 10 at-% and gradients reaching 20 at-%/nm. Two-bands $\mathbf{k}\cdot\mathbf{p}$ simulations suggest deterministic enhancement of valley splittings in steep trapezoidal $2k_0/3$ heterostructures, while the effect in $k_0$-type quantum wells is much weaker.

physics.app-ph↗

arXiv2026

Singlet-triplet oscillations in multivalley Si double quantum dots

Charge separation from the $(4,0)$ to the $(3,1)$ state in a Si/SiGe double quantum dot is commonly used for initialization of spin qubits and Pauli-spin-blockade readout. It was used in recent experiments involving creation of the $(3,1)$ singlet, and subsequent shuttling of one of the electrons. We present a theoretical description of the process of charge separation and singlet-triplet mixing, arriving at expressions for the singlet return probability that take into account experimentally observed finite probabilities of the creation of singlets with various patterns of valley occupations. In our analysis we focus on magnetic fields for which the electron spin Zeeman splitting is close to the valley splitting in one of the dots, when the spin-valley coupling causes a strong renormalization of the frequency of oscillations of singlet return probability. The latter effect has been recently used to perform valley splitting mapping by shuttling of one quantum dot to various locations with respect to the other. We give a detailed description of singlet-triplet dynamics near these spin-valley resonances and compare the results of calculations with measurements on double quantum dots in two distinct Si/SiGe heterostructures. Comparison of theory with experiments in which the presence of a few valley occupation patterns is visible, gives insight into the valley dependence of $g$-factors in these structures, providing support for a recently proposed theoretical model of this dependence. We also discuss how dephasing of singlet return probability oscillations near the spin-valley resonances is affected by valley splitting fluctuations caused by electric field noise.

cond-mat.mes-hall↗

arXiv2026

Fabrication, characterization and mechanical loading of Si/SiGe membranes for spin qubit devices

Si/SiGe heterostructures on bulk Si substrates have been shown to host high fidelity electron spin qubits. Building a scalable quantum processor would, however, benefit from further improvement of critical material properties such as the valley-splitting landscape. Flexible control of the strain field and the out-of-plane electric field $\mathcal{E}_z$ may be decisive for valley splitting enhancement in the presence of alloy disorder. We envision the Si/SiGe membrane as a versatile scientific platform for investigating intervalley scattering mechanisms which have thus far remained elusive in conventional Si/SiGe heterostructures and have the potential to yield favourable valley-splitting distributions. Here, we report the fabrication of locally etched, suspended SiGe/Si/SiGe membranes from two different heterostructures and apply the process to realize a spin-qubit shuttling device on a membrane for future valley mapping experiments. The membranes have a thickness in the micrometer range and can be metallized to form a back-gate contact for extended control over the electric field. To probe their elastic properties, the membranes are stressed by loading with a profilometer stylus at room temperature. We distinguish between linear elastic and buckling modes, each offering mechanisms through which strain can be coupled to spin qubits.

cond-mat.mes-hall↗

arXiv2026

Conveyor-mode electron shuttling through a T-junction in Si/SiGe

Conveyor-mode shuttling in gated Si/SiGe devices enables adiabatic transfer of single electrons, electron patterns and spin qubits confined in quantum dots across several microns with a scalable number of signal lines. To realize their full potential, linear shuttle lanes must connect into a two-dimensional grid with controllable routing. We introduce a T-junction device linking two independently driven shuttle lanes. Electron routing across the junction requires no extra control lines beyond the four channels per conveyor belt. We measure an inter-lane charge transfer fidelity of $F = 100.0000000^{+0}_{-9\times 10^{-7}}\,\%$ at an instantaneous electron velocity of $270\,\mathrm{mm}\,\mathrm{s}^{-1}$. The filling of 54 quantum dots is controlled by simple atomic pulses, allowing us to swap electron patterns, laying the groundwork for a native spin-qubit SWAP gate. This T-junction establishes a path towards scalable, two-dimensional quantum computing architectures with flexible spin qubit routing for quantum error correction.

cond-mat.mes-hall↗

arXiv2025

Numerical simulation of coherent spin-shuttling in a QuBus with charged defects

Recent advances in coherent conveyor-mode spin qubit shuttling are paving the way for large-scale quantum computing platforms with qubit connectivity achieved by spin qubit shuttles. We developed a simulation tool to investigate numerically the impact of device imperfections on the spin-coherence of conveyor-mode shuttling in Si/SiGe. We simulate the quantum evolution of a mobile electron spin-qubit under the influence of sparse and singly charged point defects placed in the Si/SiGe heterostructure in close proximity to the shuttle lane. We consider different locations of a single charge defect with respect to the center of the shuttle lane, multiple orbital states of the electron in the shuttle with $g$-factor differences between the orbital levels, and orbital relaxation induced by electron-phonon interaction. With this simulation framework, we identify the critical defect density of charged point defects in the heterostructure for conveyor-mode spin qubit shuttle devices and quantify the impact of a single defect on the coherence of a qubit.

cond-mat.mes-hall↗

arXiv2025

High yield, low disorder Si/SiGe heterostructures for spin qubit devices manufactured in a BiCMOS pilot line

The prospect of achieving fault-tolerant quantum computing with semiconductor spin qubits in Si/SiGe heterostructures relies on the integration of a large number of identical devices, a feat achievable through a scalable (Bi)CMOS manufacturing approach. To this end, both the gate stack and the Si/SiGe heterostructure must be of high quality, exhibiting uniformity across the wafer and consistent performance across multiple fabrication runs. Here, we report a comprehensive investigation of Si/SiGe heterostructures and gate stacks, fabricated in an industry-standard 200 mm BiCMOS pilot line. We evaluate the homogeneity and reproducibility by probing the properties of the two-dimensional electron gas (2DEG) in the shallow silicon quantum well through magnetotransport characterization of Hall bar-shaped field-effect transistors at 1.5 K. Across all the probed wafers, we observe minimal variation of the 2DEG properties, with an average maximum mobility of $(4.25\pm0.17)\times 10^{5}$ cm$^{2}$/Vs and low percolation carrier density of $(5.9\pm0.18)\times 10^{10}$ cm$^{-2}$ evidencing low disorder potential in the quantum well. The observed narrow statistical distribution of the transport properties highlights the reproducibility and the stability of the fabrication process. Furthermore, wafer-scale characterization of a selected individual wafer evidenced the homogeneity of the device performances across the wafer area. Based on these findings, we conclude that our material and processes provide a suitable platform for the development of scalable, Si/SiGe-based quantum devices.

cond-mat.mes-hall↗

arXiv2025

Industrially fabricated single-electron quantum dots in Si/Si-Ge heterostructures

This paper reports the compatibility of heterostructure-based spin qubit devices with industrial CMOS technology. It features Si/Si-Ge quantum dot devices fabricated using Infineon's 200 mm production line within a restricted thermal budget. The devices exhibit state-of-the-art charge sensing, charge noise and valley splitting characteristics, showing that industrial fabrication is not harming the heterostructure quality. These measured parameters are all correlated to spin qubit coherence and qubit gate fidelity. We describe the single electron device layout, design and its fabrication process using electron beam lithography. The incorporated standard 90 nm back-end of line flow for gate-layer independent contacting and wiring can be scaled up to multiple wiring layers for scalable quantum computing architectures. In addition, we present millikelvin characterization results. Our work exemplifies the potential of industrial fabrication methods to harness the inherent CMOS-compatibility of the Si/Si-Ge material system, despite being restricted to a reduced thermal budget. It paves the way for advanced quantum processor architectures with high yield and device quality.

cond-mat.mes-hall↗

arXiv2024

Strategies for enhancing spin-shuttling fidelities in Si/SiGe quantum wells with random-alloy disorder

Coherent coupling between distant qubits is needed for any scalable quantum computing scheme. In quantum dot systems, one proposal for long-distance coupling is to coherently transfer electron spins across a chip in a moving potential. Here, we use simulations to study challenges for spin shuttling in Si/SiGe heterostructures caused by the valley degree of freedom. We show that for devices with valley splitting dominated by alloy disorder, one can expect to encounter pockets of low valley splitting, given a long-enough shuttling path. At such locations, inter-valley tunneling leads to dephasing of the spin wavefunction, substantially reducing the shuttling fidelity. We show how to mitigate this problem by modifying the heterostructure composition, or by varying the vertical electric field, the shuttling velocity, the shape and size of the dot, or the shuttling path. We further show that combinations of these strategies can reduce the shuttling infidelity by several orders of magnitude, putting shuttling fidelities sufficient for error correction within reach.

cond-mat.mes-hall↗

arXiv2024

Long distance spin shuttling enabled by few-parameter velocity optimization

Spin qubit shuttling via moving conveyor-mode quantum dots in Si/SiGe offers a promising route to scalable miniaturized quantum computing. Recent modeling of dephasing via valley degrees of freedom and well disorder dictate a slow shutting speed which seems to limit errors to above correction thresholds if not mitigated. We increase the precision of this prediction, showing that typical errors for 10 $μ$m shuttling at constant speed results in O(1) error, using fast, automatically differentiable numerics and including improved disorder modeling and potential noise ranges. However, remarkably, we show that these errors can be brought to well below fault-tolerant thresholds using trajectory shaping with very simple parametrization with as few as 4 Fourier components, well within the means for experimental in-situ realization, and without the need for targeting or knowing the location of valley near degeneracies.

quant-ph↗

arXiv2024

Scalable Parity Architecture With a Shuttling-Based Spin Qubit Processor

Motivated by the prospect of a two-dimensional square-lattice geometry for semiconductor spin qubits, we explore the realization of the Parity Architecture with quantum dots (QDs). We present sequences of spin shuttling and quantum gates that implement the Parity Quantum Approximate Optimization Algorithm (QAOA) on a lattice constructed of identical unit cells, such that the circuit depth is always constant. We further develop a detailed error model for a hardware-specific analysis of the Parity Architecture and we estimate the errors during one round of Parity QAOA. The model includes a general description of the shuttling errors as a function of the probability distribution function of the valley splitting, which is the main limitation for the performance. We compare our approach to a superconducting transmon qubit chip and we find that with high-fidelity spin shuttling the performance of the spin qubits is competitive or even exceeds the results of the transmons. Finally, we discuss the possibility of decoding the logical quantum state and of quantum error mitigation. We find that already with near-term spin qubit devices a sufficiently low physical error probability can be expected to reliably perform Parity QAOA with a short depth in a regime where the success probability compares favorably to standard QAOA.

quant-ph↗

arXiv2024

Optimizing ToF-SIMS Depth Profiles of Semiconductor Heterostructures

The continuous technological development of electronic devices and the introduction of new materials leads to ever greater demands on the fabrication of semiconductor heterostructures and their characterization. This work focuses on optimizing Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) depth profiles of semiconductor heterostructures aiming at a minimization of measurement-induced profile broadening. As model system, a state-of-the-art Molecular Beam Epitaxy (MBE) grown multilayer homostructure consisting of $^{\textit{nat}}$Si/$^{28}$Si bilayers with only 2 nm in thickness is investigated while varying the most relevant sputter parameters. Atomic concentration-depth profiles are determined and an error function based description model is used to quantify layer thicknesses as well as profile broadening. The optimization process leads to an excellent resolution of the multilayer homostructure. The results of this optimization guide to a ToF-SIMS analysis of another MBE grown heterostructure consisting of a strained and highly purified $^{28}$Si layer sandwiched between two Si$_{0.7}$Ge$_{0.3}$ layers. The sandwiched $^{28}$Si layer represents a quantum well that has proven to be an excellent host for the implementation of electron-spin qubits.

physics.app-ph↗

arXiv2024

Atomistic compositional details and their importance for spin qubits in isotope-purified silicon-germanium quantum wells

Understanding crystal characteristics down to the atomistic level increasingly emerges as a crucial insight for creating solid state platforms for qubits with reproducible and homogeneous properties. Here, isotope composition depth profiles in a SiGe/$^{28}$Si/SiGe heterostructure are analyzed with atom probe tomography (APT) and time-of-flight secondary-ion mass spectrometry. Spin-echo dephasing times $T_2^{echo}=128 μs$ and valley energy splittings around $200 μeV$ have been observed for single spin qubits in this quantum well (QW) heterostructure, pointing towards the suppression of qubit decoherence through hyperfine interaction or via scattering between valley states. The concentration of nuclear spin-carrying $^{29}$Si is 50 ppm in the $^{28}$Si QW. APT allows to uncover that both the top SiGe/$^{28}$Si and the bottom $^{28}$Si/SiGe interfaces of the QW are shaped by epitaxial growth front segregation signatures on a few monolayer scale. A subsequent thermal treatment broadens the top interface by about two monolayers, while the width of the bottom interface remains unchanged. Using a tight-binding model including SiGe alloy disorder, these experimental results suggest that the combination of the slightly thermally broadened top interface and of a minimal Ge concentration of $0.3 \%$ in the QW, resulting from segregation, is instrumental for the observed large valley splitting. Minimal Ge additions $< 1 \%$, which get more likely in thin QWs, will hence support high valley splitting without compromising coherence times. At the same time, taking thermal treatments during device processing as well as the occurrence of crystal growth characteristics into account seems important for the design of reproducible qubit properties.

cond-mat.mes-hall↗

arXiv2024

Noise reduction by bias cooling in gated Si/SixGe1-x quantum dots

Silicon-Germanium heterostructures are a promising quantum circuit platform, but crucial aspects as the long-term charge dynamics and cooldown-to-cooldown variations are still widely unexplored quantitatively. In this letter we present the results of an extensive bias cooling study performed on gated silicon-germanium quantum dots with an Al2O3-dielectric. Over 80 cooldowns were performed in the course of our investigations. The performance of the devices is assessed by low-frequency charge noise measurements in the band of 200 micro Hertz to 10 milli Hertz. We measure the total noise power as a function of the applied voltage during cooldown in four different devices and find a minimum in noise at 0.7V bias cooling voltage for all observed samples. We manage to decrease the total noise power median by a factor of 6 and compute a reduced tunneling current density using Schrödinger-Poisson simulations. Furthermore, we show the variation in noise from the same device in the course of eleven different cooldowns performed under the nominally same conditions.

cond-mat.mes-hall↗