arXiv subjects

Lining Zhang

Publications and source records attributed to Lining Zhang.

16 recordsLinked to original sources

arXiv2026

A Novel Decoupling Method for Investigating Distinct Domain Evolution in Ferroelectric Film

Conventional polarization characterization techniques provide only the averaged response of ferroelectric films, limiting the investigation of domain-dependent reliability mechanisms in HfO2-based ferroelectrics. In this work, a new domain decoupling method is proposed to separately analyze ferroelectric domains with distinct switching behaviors. A three-domain model consisting of upward non-switchable domains, downward non-switchable domains, and switchable domains (Pd) is first introduced to describe heterogeneous domain populations during electrical cycling. By combining complementary switching-current measurements, the responses of different domain populations can be selectively extracted and reconstructed. The proposed method enables quantitative tracking of individual domain populations during cycling. As a demonstration, the method is further applied to analyze the time-dependent evolution of domain populations after electrical cycling. This approach provides a new route for investigating imprint, fatigue, and other reliability-related phenomena in ferroelectric devices.

cond-mat.mtrl-sci↗

arXiv2026

From 50% to Mastery in 3 Days: A Low-Resource SOP for Localizing Graduate-Level AI Tutors via Shadow-RAG

Deploying high-fidelity AI tutors in schools is often blocked by the Resource Curse -- the need for expensive cloud GPUs and massive data engineering. In this practitioner report, we present a replicable Standard Operating Procedure that breaks this barrier. Using a Vision-Language Model data cleaning strategy and a novel Shadow-RAG architecture, we localized a graduate-level Applied Mathematics tutor using only 3 person-days of non-expert labor and open-weights 32B models deployable on a single consumer-grade GPU. Our pilot study on a full graduate-level final exam reveals a striking emergence phenomenon: while both zero-shot baselines and standard retrieval stagnate around 50-60% accuracy across model generations, the Shadow Agent, which provides structured reasoning guidance, triggers a massive capability surge in newer 32B models, boosting performance from 74% (Naive RAG) to mastery level (90%). In contrast, older models see only modest gains (~10%). This suggests that such guidance is the key to unlocking the latent power of modern small language models. This work offers a cost-effective, scientifically grounded blueprint for ubiquitous AI education.

cs.AI↗

arXiv2026

CellE: Automated Standard Cell Library Extension via Equality Saturation

Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.

cs.AR↗

arXiv2025

Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization

With the diminishing return from Moore's Law, system-technology co-optimization (STCO) has emerged as a promising approach to sustain the scaling trends in the VLSI industry. By bridging the gap between system requirements and technology innovations, STCO enables customized optimizations for application-driven system architectures. However, existing research lacks sufficient discussion on efficient STCO methodologies, particularly in addressing the information gap across design hierarchies and navigating the expansive cross-layer design space. To address these challenges, this paper presents Orthrus, a dual-loop automated framework that synergizes system-level and technology-level optimizations. At the system level, Orthrus employs a novel mechanism to prioritize the optimization of critical standard cells using system-level statistics. It also guides technology-level optimization via the normal directions of the Pareto frontier efficiently explored by Bayesian optimization. At the technology level, Orthrus leverages system-aware insights to optimize standard cell libraries. It employs a neural network-assisted enhanced differential evolution algorithm to efficiently optimize technology parameters. Experimental results on 7nm technology demonstrate that Orthrus achieves 12.5% delay reduction at iso-power and 61.4% power savings at iso-delay over the baseline approaches, establishing new Pareto frontiers in STCO.

cs.AR↗

arXiv2025

Overview of Dialog System Evaluation Track: Dimensionality, Language, Culture and Safety at DSTC 12

The rapid advancement of Large Language Models (LLMs) has intensified the need for robust dialogue system evaluation, yet comprehensive assessment remains challenging. Traditional metrics often prove insufficient, and safety considerations are frequently narrowly defined or culturally biased. The DSTC12 Track 1, "Dialog System Evaluation: Dimensionality, Language, Culture and Safety," is part of the ongoing effort to address these critical gaps. The track comprised two subtasks: (1) Dialogue-level, Multi-dimensional Automatic Evaluation Metrics, and (2) Multilingual and Multicultural Safety Detection. For Task 1, focused on 10 dialogue dimensions, a Llama-3-8B baseline achieved the highest average Spearman's correlation (0.1681), indicating substantial room for improvement. In Task 2, while participating teams significantly outperformed a Llama-Guard-3-1B baseline on the multilingual safety subset (top ROC-AUC 0.9648), the baseline proved superior on the cultural subset (0.5126 ROC-AUC), highlighting critical needs in culturally-aware safety. This paper describes the datasets and baselines provided to participants, as well as submission evaluation results for each of the two proposed subtasks.

cs.CL↗

arXiv2025

Exploring Active Learning for Semiconductor Defect Segmentation

The development of X-Ray microscopy (XRM) technology has enabled non-destructive inspection of semiconductor structures for defect identification. Deep learning is widely used as the state-of-the-art approach to perform visual analysis tasks. However, deep learning based models require large amount of annotated data to train. This can be time-consuming and expensive to obtain especially for dense prediction tasks like semantic segmentation. In this work, we explore active learning (AL) as a potential solution to alleviate the annotation burden. We identify two unique challenges when applying AL on semiconductor XRM scans: large domain shift and severe class-imbalance. To address these challenges, we propose to perform contrastive pretraining on the unlabelled data to obtain the initialization weights for each AL cycle, and a rareness-aware acquisition function that favors the selection of samples containing rare classes. We evaluate our method on a semiconductor dataset that is compiled from XRM scans of high bandwidth memory structures composed of logic and memory dies, and demonstrate that our method achieves state-of-the-art performance.

cs.CV↗

arXiv2025

Exploring Spatial Diversity for Region-based Active Learning

State-of-the-art methods for semantic segmentation are based on deep neural networks trained on large-scale labeled datasets. Acquiring such datasets would incur large annotation costs, especially for dense pixel-level prediction tasks like semantic segmentation. We consider region-based active learning as a strategy to reduce annotation costs while maintaining high performance. In this setting, batches of informative image regions instead of entire images are selected for labeling. Importantly, we propose that enforcing local spatial diversity is beneficial for active learning in this case, and to incorporate spatial diversity along with the traditional active selection criterion, e.g., data sample uncertainty, in a unified optimization framework for region-based active learning. We apply this framework to the Cityscapes and PASCAL VOC datasets and demonstrate that the inclusion of spatial diversity effectively improves the performance of uncertainty-based and feature diversity-based active learning methods. Our framework achieves $95\%$ performance of fully supervised methods with only $5-9\%$ of the labeled pixels, outperforming all state-of-the-art region-based active learning methods for semantic segmentation.

cs.CV↗

arXiv2025

AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models

Arithmetic circuits, such as adders and multipliers, are fundamental components of digital systems, directly impacting the performance, power efficiency, and area footprint. However, optimizing these circuits remains challenging due to the vast design space and complex physical constraints. While recent deep learning-based approaches have shown promise, they struggle to consistently explore high-potential design variants, limiting their optimization efficiency. To address this challenge, we propose AC-Refiner, a novel arithmetic circuit optimization framework leveraging conditional diffusion models. Our key insight is to reframe arithmetic circuit synthesis as a conditional image generation task. By carefully conditioning the denoising diffusion process on target quality-of-results (QoRs), AC-Refiner consistently produces high-quality circuit designs. Furthermore, the explored designs are used to fine-tune the diffusion model, which focuses the exploration near the Pareto frontier. Experimental results demonstrate that AC-Refiner generates designs with superior Pareto optimality, outperforming state-of-the-art baselines. The performance gain is further validated by integrating AC-Refiner into practical applications.

cs.AR↗

arXiv2025

Design Optimization of Flip FET Standard Cells with Dual-sided Pins for Ultimate Scaling

Recently, we proposed a novel transistor architecture for 3D stacked FETs called Flip FET (FFET), featuring N/P transistors back-to-back stacked and dual-sided interconnects. With dual-sided power rails and signal tracks, FFET can achieve an aggressive 2.5T cell height. As a tradeoff, the complex structure and limited numbers of M0 tracks could limit the standard cell design. As a solution, multiple innovations were introduced and examined in this work. Based on an advanced node design rule, several unique building blocks in FFET such as drain merge (DM), gate merge (GM), field drain merge (FDM) and buried signal track (BST) were investigated. Other key design concepts of multi-row, split gate and dummy gate insertion (DG) were also carefully studied, delivering around 35.6% area reduction compared with 3T CFET. Furthermore, the symmetric design of FFET has unique superiority over CFET thanks to the separate N/P logic on two sides of the wafer and their connections using DM and GM. New routing scheme with dual-sided output pins on both wafer frontside (FS) and backside (BS) was proposed for the first time. Finally, we conducted a comprehensive evaluation on complex cell design, taking AOI22 as an example. New strategies were proposed and examined. The FDM design is identified as the best, outperforming the BST and dummy gate design by 1.93% and 5.13% for the transition delay.

cond-mat.mes-hall↗

arXiv2025

DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators

Multipliers and multiply-accumulators (MACs) are fundamental building blocks for compute-intensive applications such as artificial intelligence. With the diminishing returns of Moore's Law, optimizing multiplier performance now necessitates process-aware architectural innovations rather than relying solely on technology scaling. In this paper, we introduce DOMAC, a novel approach that employs differentiable optimization for designing multipliers and MACs at specific technology nodes. DOMAC establishes an analogy between optimizing multi-staged parallel compressor trees and training deep neural networks. Building on this insight, DOMAC reformulates the discrete optimization challenge into a continuous problem by incorporating differentiable timing and area objectives. This formulation enables us to utilize existing deep learning toolkit for highly efficient implementation of the differentiable solver. Experimental results demonstrate that DOMAC achieves significant enhancements in both performance and area efficiency compared to state-of-the-art baselines and commercial IPs in multiplier and MAC designs.

cs.AR↗

arXiv2025

DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization

The proliferation of deep learning accelerators calls for efficient and cost-effective hardware design solutions, where parameterized modular hardware generator and electronic design automation (EDA) tools play crucial roles in improving productivity and final Quality-of-Results (QoR). To strike a good balance across multiple QoR of interest (e.g., performance, power, and area), the designers need to navigate a vast design space, encompassing tunable parameters for both hardware generator and EDA synthesis tools. However, the significant time for EDA tool invocations and complex interplay among numerous design parameters make this task extremely challenging, even for experienced designers. To address these challenges, we introduce DiffuSE, a diffusion-driven design space exploration framework for cross-layer optimization of DNN accelerators. DiffuSE leverages conditional diffusion models to capture the inverse, one-to-many mapping from QoR objectives to parameter combinations, allowing for targeted exploration within promising regions of the design space. By carefully selecting the conditioning QoR values, the framework facilitates an effective trade-off among multiple QoR metrics in a sample-efficient manner. Experimental results under 7nm technology demonstrate the superiority of the proposed framework compared to previous arts.

cs.AR↗

arXiv2024

A Novel Energy-Efficient Salicide-Enhanced Tunnel Device Technology Based on 300mm Foundry Platform Towards AIoT Applications

This work demonstrates a novel energy-efficient tunnel FET (TFET)-CMOS hybrid foundry platform for ultralow-power AIoT applications. By utilizing the proposed monolithic integration process, the novel complementary n and p-type Si TFET technology with dopant segregated source junction and self-aligned drain underlap design is successfully integrated into a 300mm CMOS baseline process without CMOS performance penalty and any new materials, experimentally demonstrating the large Ion and record high Ion/Ioff ratio of 10^7 among TFETs by industry-manufacturers. The device performance and variability are also co-optimized for high-volume production. Further circuit-level implementations are presented based on the calibrated compact model. The proposed TFET-CMOS hybrid logic and SRAM topologies show significant energy efficiency improvement with comparable operation speed compared with standard CMOS circuits, indicating its great potential for power-constraint AIoT applications.

cond-mat.mes-hall↗

arXiv2024

On the Role of Summary Content Units in Text Summarization Evaluation

At the heart of the Pyramid evaluation method for text summarization lie human written summary content units (SCUs). These SCUs are concise sentences that decompose a summary into small facts. Such SCUs can be used to judge the quality of a candidate summary, possibly partially automated via natural language inference (NLI) systems. Interestingly, with the aim to fully automate the Pyramid evaluation, Zhang and Bansal (2021) show that SCUs can be approximated by automatically generated semantic role triplets (STUs). However, several questions currently lack answers, in particular: i) Are there other ways of approximating SCUs that can offer advantages? ii) Under which conditions are SCUs (or their approximations) offering the most value? In this work, we examine two novel strategies to approximate SCUs: generating SCU approximations from AMR meaning representations (SMUs) and from large language models (SGUs), respectively. We find that while STUs and SMUs are competitive, the best approximation quality is achieved by SGUs. We also show through a simple sentence-decomposition baseline (SSUs) that SCUs (and their approximations) offer the most value when ranking short summaries, but may not help as much when ranking systems or longer summaries.

cs.CL↗

arXiv2022

Needle in a Haystack: An Analysis of High-Agreement Workers on MTurk for Summarization

To prevent the costly and inefficient use of resources on low-quality annotations, we want a method for creating a pool of dependable annotators who can effectively complete difficult tasks, such as evaluating automatic summarization. Thus, we investigate the recruitment of high-quality Amazon Mechanical Turk workers via a two-step pipeline. We show that we can successfully filter out subpar workers before they carry out the evaluations and obtain high-agreement annotations with similar constraints on resources. Although our workers demonstrate a strong consensus among themselves and CloudResearch workers, their alignment with expert judgments on a subset of the data is not as expected and needs further training in correctness. This paper still serves as a best practice for the recruitment of qualified annotators in other challenging annotation tasks.

cs.CL↗

arXiv2016

Interlayer Conductance of Graphene with Multiple Transfer Process

Electrical properties of multi-layer graphene are subject to variations due to random interlayer alignments. In this work we reported graphene interlayer conductance without special layer aligning. Ohmic contacts between two graphene layers are observed with resistance variations of more than one order. With Raman spectroscopy we identify that the lattice angle between twisted graphene layers is the key variation source. The angular dependence and temperature dependence of the interlayer conductance suggest that a phonon assistant tunneling mechanism is valid for the interlayer transport of graphene prepared by multiple transfer process. We finally derive that the multi-layer graphene resistance shows an exponential-like distribution due to the random interlayer misalignments.

cond-mat.mes-hall↗

arXiv2015

Quantum Transport Simulation of III-V TFETs with Reduced-Order K.P Method

III-V tunneling field-effect transistors (TFETs) offer great potentials in future low-power electronics application due to their steep subthreshold slope and large "on" current. Their 3D quantum transport study using non-equilibrium Green's function method is computationally very intensive, in particular when combined with multiband approaches such as the eight-band K.P method. To reduce the numerical cost, an efficient reduced-order method is developed in this article and applied to study homojunction InAs and heterojunction GaSb-InAs nanowire TFETs. Device performances are obtained for various channel widths, channel lengths, crystal orientations, doping densities, source pocket lengths, and strain conditions.

cond-mat.mes-hall↗