arXiv subjects

Louis Hutin

Publications and source records attributed to Louis Hutin.

At least 19 recordsLinked to original sources

arXiv2026

Deterministic control of the probabilistic phase dynamics in injection-locked spin-torque nano-oscillators

Spin-torque nano-oscillators (STNOs) inherently exhibit thermally driven phase fluctuations that render their dynamics truly stochastic. Here, we demonstrate that, despite this intrinsic randomness, the probability of occupying each phase state can be deterministically and continuously programmed. We experimentally investigate a vortex-based STNO operating under second-harmonic injection-locking, where the oscillator phase settles into two degenerate attractors separated by $\pi$ and undergoes thermally activated phase jumps. By applying a weak radio-frequency perturbation at the free-running frequency, we tune the phase-jump rates between the two attractors without suppressing the fluctuations, achieving continuous probability control from the unbiased limit to values approaching 0 or 1. The bias phase selects which attractor is favored while the bias amplitude sets the strength of the imbalance, providing two complementary control knobs within a single nanoscale device. A phase-reduced description based on an effective quasipotential quantitatively accounts for the observations. These results establish injection-locked STNOs as programmable stochastic elements and provide a hardware primitive for probabilistic computing, Ising machines, and brain-inspired computing architectures.

cond-mat.mes-hall↗

arXiv2026

Orbital and Spin-Orbit Torque Interplay in Ta/W-based Magnetic Tunnel Junctions with Vertical Non-local Switching

Spin-orbit torque (SOT) enables ultra-fast, energy-efficient magnetization switching, making it a promising mechanism for introducing MRAMs for cache memory applications. However, current SOT-MRAM devices face write efficiency limitations, with charge-to-spin conversion ($\xi_{DL}$) reaching $\sim$ 45\%, far below the projected $\sim$ 80\% needed to comply with the current delivery of advanced transistor nodes. Recent advances in orbital current physics, evidenced in a wide class of materials, offer a path to enhance $\xi_{DL}$. Here, we study the Ta(3-30 nm)\slash W(1-4 nm) system, revealing a large additional spin-orbit torque contribution arising from Ta, a four-fold increase compared to the spin Hall effect in Ta alone, attributed to the orbital Hall contribution. This system exhibits larger $\xi_{DL}$ than W-based SOT systems with more robust perpendicular magnetic anisotropy and compatibility with 400$^\circ$C annealing. Leveraging these advantages, we integrate the Ta/W system into 3-terminal SOT-MTJ devices, showing a level of performance similar to that of W-based systems. Our results show that orbital physics can be easily integrated into SOT-MTJ systems, offering a viable strategy to enhance SOT-MRAM efficiency. In addition, we propose and demonstrate a proof-of-concept for vertical non-local switching of SOT-MTJ using orbital torques, simplifying bottom-pinned SOT-MRAM fabrication.

cond-mat.mes-hall↗

arXiv2025

Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine

Hardware implementations of the Ising model offer promising solutions to large-scale optimization tasks. In the literature, various nanodevices have been shown to emulate the spin dynamics for such Ising machines with remarkable effectiveness. Other nanodevices have been shown to implement spin-spin coupling with compact footprint and minimal energy dissipation. However, an ideal Ising machine would associate both types of nanodevices, and they must operate synergistically to support annealing: a progressive reduction of machine stochasticity that allows it to settle to energy minimum. Here, we report an Ising machine that combines two nanotechnologies: memristor crossbar -- storing multi-level couplings -- and stochastic magnetic tunnel junction (SMTJ), acting as thermally driven spins. Because the same read voltage that interrogates the crossbar also biases the SMTJs, increasing this voltage automatically lowers the effective temperature of the machine, providing an intrinsic, nearly circuit-free annealing technique. Operating at zero magnetic field, our prototype consistently reaches the global optimum of a 24-vertex weighted MAX-CUT and a 10-vertex, three-color graph-coloring problem. Given that both nanotechnologies in our demonstrator are CMOS-integrated, this approach is compatible with advanced 3D integration, offering a scalable pathway toward compact, fast, and energy-efficient large-scale Ising solvers.

cs.ET↗

arXiv2024

Roadmap to Neuromorphic Computing with Emerging Technologies

The roadmap is organized into several thematic sections, outlining current computing challenges, discussing the neuromorphic computing approach, analyzing mature and currently utilized technologies, providing an overview of emerging technologies, addressing material challenges, exploring novel computing concepts, and finally examining the maturity level of emerging technologies while determining the next essential steps for their advancement.

eess.SP↗

arXiv2023

Gate reflectometry in dense quantum dot arrays

Silicon quantum devices are maturing from academic single- and two-qubit devices to industrially-fabricated dense quantum-dot (QD) arrays, increasing operational complexity and the need for better pulsed-gate and readout techniques. We perform gate-voltage pulsing and gate-based reflectometry measurements on a dense 2$\times$2 array of silicon quantum dots fabricated in a 300-mm-wafer foundry. Utilizing the strong capacitive couplings within the array, it is sufficient to monitor only one gate electrode via high-frequency reflectometry to establish single-electron occupation in each of the four dots and to detect single-electron movements with high bandwidth. A global top-gate electrode adjusts the overall tunneling times, while linear combinations of side-gate voltages yield detailed charge stability diagrams. To test for spin physics and Pauli spin blockade at finite magnetic fields, we implement symmetric gate-voltage pulses that directly reveal bidirectional interdot charge relaxation as a function of the detuning between two dots. Charge sensing within the array can be established without the involvement of adjacent electron reservoirs, important for scaling such split-gate devices towards longer 2$\times$N arrays. Our techniques may find use in the scaling of few-dot spin-qubit devices to large-scale quantum processors.

cond-mat.mes-hall↗

arXiv2022

Probing charge noise in few electron CMOS quantum dots

Charge noise is one of the main sources of environmental decoherence for spin qubits in silicon, presenting a major obstacle in the path towards highly scalable and reproducible qubit fabrication. Here we demonstrate in-depth characterization of the charge noise environment experienced by a quantum dot in a CMOS-fabricated silicon nanowire. We probe the charge noise for different quantum dot configurations, finding that it is possible to tune the charge noise over two orders of magnitude, ranging from 1 ueV^2 to 100 ueV^2. In particular, we show that the top interface and the reservoirs are the main sources of charge noise and their effect can be mitigated by controlling the quantum dot extension. Additionally, we demonstrate a novel method for the measurement of the charge noise experienced by a quantum dot in the few electron regime. We measure a comparatively higher charge noise value of 40 ueV^2 at the first electron, and demonstrate that the charge noise is highly dependent on the electron occupancy of the quantum dot.

cond-mat.mes-hall↗

arXiv2021

Quantum Dot-Based Parametric Amplifiers

Josephson parametric amplifiers (JPAs) approaching quantum-limited noise performance have been instrumental in enabling high fidelity readout of superconducting qubits and, recently, semiconductor quantum dots (QDs). We propose that the quantum capacitance arising in electronic two-level systems (the dual of Josephson inductance) can provide an alternative dissipation-less non-linear element for parametric amplification. We experimentally demonstrate phase-sensitive parametric amplification using a QD-reservoir electron transition in a CMOS nanowire split-gate transistor embedded in a 1.8~GHz superconducting lumped-element microwave cavity, achieving parametric gains of -3 to +3 dB, limited by Sisyphus dissipation. Using a semi-classical model, we find an optimised design within current technological capabilities could achieve gains and bandwidths comparable to JPAs, while providing complementary specifications with respect to integration in semiconductor platforms or operation at higher magnetic fields.

cond-mat.mes-hall↗

arXiv2021

Non-reciprocal Pauli Spin Blockade in a Silicon Double Quantum Dot

Spin qubits in gate-defined silicon quantum dots are receiving increased attention thanks to their potential for large-scale quantum computing. Readout of such spin qubits is done most accurately and scalably via Pauli spin blockade (PSB), however various mechanisms may lift PSB and complicate readout. In this work, we present an experimental observation of a new, highly prevalent PSB-lifting mechanism in a silicon double quantum dot due to incoherent tunneling between different spin manifolds. Through dispersively-detected magnetospectroscopy of the double quantum dot in 16 charge configurations, we find the mechanism to be energy-level selective and non-reciprocal for neighbouring charge configurations. Additionally, using input-output theory we report a large coupling of different electron spin manifolds of 7.90 $μ$eV, the largest reported to date, indicating an enhanced spin-orbit coupling which may enable all-electrical qubit control.

cond-mat.mes-hall↗

arXiv2021

Large dispersive interaction between a CMOS double quantum dot and microwave photons

We report fast charge state readout of a double quantum dot in a CMOS split-gate silicon nanowire transistor via the large dispersive interaction with microwave photons in a lumped-element resonator formed by hybrid integration with a superconducting inductor. We achieve a coupling rate $g_0/(2π) = 204 \pm 2$ MHz by exploiting the large interdot gate lever arm of an asymmetric split-gate device, $α=0.72$, and by inductively coupling to the resonator to increase its impedance, $Z_\text{r}=560~Ω$. In the dispersive regime, the large coupling strength at the double quantum dot hybridisation point produces a frequency shift comparable to the resonator linewidth, the optimal setting for maximum state visibility. We exploit this regime to demonstrate rapid dispersive readout of the charge degree of freedom, with a SNR of 3.3 in 50 ns. In the resonant regime, the fast charge decoherence rate precludes reaching the strong coupling regime, but we show a clear route to spin-photon circuit quantum electrodynamics using hybrid CMOS systems.

cond-mat.mes-hall↗

arXiv2021

Dispersively probed microwave spectroscopy of a silicon hole double quantum dot

Owing to ever increasing gate fidelities and to a potential transferability to industrial CMOS technology, silicon spin qubits have become a compelling option in the strive for quantum computation. In a scalable architecture, each spin qubit will have to be finely tuned and its operating conditions accurately determined. In this prospect, spectroscopic tools compatible with a scalable device layout are of primary importance. Here we report a two-tone spectroscopy technique providing access to the spin-dependent energy-level spectrum of a hole double quantum dot defined in a split-gate silicon device. A first GHz-frequency tone drives electric-dipole spin resonance enabled by the valence-band spin-orbit coupling. A second lower-frequency tone (approximately 500 MHz) allows for dispersive readout via rf-gate reflectometry. We compare the measured dispersive response to the linear response calculated in an extended Jaynes-Cummings model and we obtain characteristic parameters such as g-factors and tunnel/spin-orbit couplings for both even and odd occupation.

cond-mat.mes-hall↗

arXiv2020

Remote capacitive sensing in two-dimension quantum-dot arrays

We investigate gate-defined quantum dots in silicon on insulator nanowire field-effect transistors fabricated using a foundry-compatible fully-depleted silicon-on-insulator (FD-SOI) process. A series of split gates wrapped over the silicon nanowire naturally produces a $2\times n$ bilinear array of quantum dots along a single nanowire. We begin by studying the capacitive coupling of quantum dots within such a 2$\times$2 array, and then show how such couplings can be extended across two parallel silicon nanowires coupled together by shared, electrically isolated, 'floating' electrodes. With one quantum dot operating as a single-electron-box sensor, the floating gate serves to enhance the charge sensitivity range, enabling it to detect charge state transitions in a separate silicon nanowire. By comparing measurements from multiple devices we illustrate the impact of the floating gate by quantifying both the charge sensitivity decay as a function of dot-sensor separation and configuration within the dual-nanowire structure.

cond-mat.mes-hall↗

arXiv2020

Single-electron operation of a silicon-CMOS 2x2 quantum dot array with integrated charge sensing

The advanced nanoscale integration available in silicon complementary metal-oxide-semiconductor (CMOS) technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot formation and spin blockade in CMOS foundry-compatible devices are encouraging, but results are yet to match the control of individual electrons demonstrated in university-fabricated multi-gate designs. We show here that the charge state of quantum dots formed in a CMOS nanowire device can be sensed by using floating gates to electrostatically couple it to a remote single electron transistor (SET) formed in an adjacent nanowire. By biasing the nanowire and gates of the remote SET with respect to the nanowire hosting the quantum dots, we controllably form ancillary quantum dots under the floating gates, thus enabling the demonstration of independent control over charge transitions in a quadruple (2x2) quantum dot array. This device overcomes the limitations associated with measurements based on tunnelling transport through the dots and permits the sensing of all charge transitions, down to the last electron in each dot. We use effective mass theory to investigate the necessary optimization of the device parameters in order to achieve the tunnel rates required for spin-based quantum computation.

cond-mat.mes-hall↗

arXiv2020

Single-electron control in a foundry-fabricated two-dimensional qubit array

Silicon spin qubits have achieved high-fidelity one- and two-qubit gates, above error correction thresholds, promising an industrial route to fault-tolerant quantum computation. A significant next step for the development of scalable multi-qubit processors is the operation of foundry-fabricated, extendable two-dimensional (2D) arrays. In gallium arsenide, 2D quantum-dot arrays recently allowed coherent spin operations and quantum simulations. In silicon, 2D arrays have been limited to transport measurements in the many-electron regime. Here, we operate a foundry-fabricated silicon 2x2 array in the few-electron regime, achieving single-electron occupation in each of the four gate-defined quantum dots, as well as reconfigurable single, double, and triple dots with tunable tunnel couplings. Pulsed-gate and gate-reflectometry techniques permit single-electron manipulation and single-shot charge readout, while the two-dimensionality allows the spatial exchange of electron pairs. The compact form factor of such arrays, whose foundry fabrication can be extended to larger 2xN arrays, along with the recent demonstration of coherent spin control and readout, paves the way for dense qubit arrays for quantum computation and simulation.

cond-mat.mes-hall↗

arXiv2020

Charge detection in an array of CMOS quantum dots

The recent development of arrays of quantum dots in semiconductor nanostructures highlights the progress of quantum devices toward large scale. However, how to realize such arrays on a scalable platform such as silicon is still an open question. One of the main challenge resides in the detection of charges within the array. It is a prerequisite functionality to initialize a desired charge state and readout spins through spin-to-charge conversion mechanisms. In this paper, we use two methods based on either a single-lead charge detector, or a reprogrammable single electron transistor. Thanks to these methods, we study the charge dynamics and sensitivity by performing single shot detection of the charge. Finally, we can probe the charge stability at any node of a linear array and assess the Coulomb disorder in the structure. We find an electrochemical potential fluctuation induced by charge noise comparable to that reported in other silicon quantum dots.

cond-mat.mes-hall↗

arXiv2019

All-Electrical Control of an Electron Spin/Valley Quantum Bit in SOI CMOS Technology

We fabricated Quantum Dot (QD) devices using a standard SOI CMOS process flow, and demonstrated that the spin of confined electrons could be controlled via a local electrical-field excitation, owing to inter-valley spin-orbit coupling. We discuss that modulating the confinement geometry via an additional electrode may enable switching a quantum bit (qubit) between an electrically-addressable valley configuration and a protected spin configuration. This proposed scheme bears relevance to improve the trade-off between fast operations and slow decoherence for quantum computing on a Si qubit platform. Finally, we evoke the impact of process-induced variability on the operating bias range.

cond-mat.mes-hall↗

arXiv2019

A Spin Quintet in a Silicon Double Quantum Dot: Spin Blockade and Relaxation

Spins in gate-defined silicon quantum dots are promising candidates for implementing large-scale quantum computing. To read the spin state of these qubits, the mechanism that has provided the highest fidelity is spin-to-charge conversion via singlet-triplet spin blockade, which can be detected in-situ using gate-based dispersive sensing. In systems with a complex energy spectrum, like silicon quantum dots, accurately identifying when singlet-triplet blockade occurs is hence of major importance for scalable qubit readout. In this work, we present a description of spin blockade physics in a tunnel-coupled silicon double quantum dot defined in the corners of a split-gate transistor. Using gate-based magnetospectroscopy, we report successive steps of spin blockade and spin blockade lifting involving spin states with total spin angular momentum up to $S=3$. More particularly, we report the formation of a hybridized spin quintet state and show triplet-quintet and quintet-septet spin blockade. This enables studies of the quintet relaxation dynamics from which we find $T_1 \sim 4 ~μs$. Finally, we develop a quantum capacitance model that can be applied generally to reconstruct the energy spectrum of a double quantum dot including the spin-dependent tunnel couplings and the energy splitting between different spin manifolds. Our results open for the possibility of using Si CMOS quantum dots as a tuneable platform for studying high-spin systems.

cond-mat.mes-hall↗

arXiv2018

Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2\,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4\,K and 4.2\,K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77\,K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

cond-mat.mes-hall↗

arXiv2018

Gate-Based High Fidelity Spin Read-out in a CMOS Device

The engineering of electron spin qubits in a compact unit cell embedding all quantum functionalities is mandatory for large scale integration. In particular, the development of a high-fidelity and scalable spin readout method remains an open challenge. Here we demonstrate high-fidelity and robust spin readout based on gate reflectometry in a CMOS device comprising one qubit dot and one ancillary dot coupled to an electron reservoir to perform readout. This scalable method allows us to read out a spin with a fidelity above 99% for 1 ms integration time. To achieve such fidelity, we exploit a latched spin blockade mechanism that requires electron exchange between the ancillary dot and the reservoir. We show that the demonstrated high read-out fidelity is fully preserved up to 0.5 K. This results holds particular relevance for the future co-integration of spin qubits and classical control electronics.

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