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M. Jagadesh Kumar

Publications and source records attributed to M. Jagadesh Kumar.

30 records · Page 2Linked to original sources
arXiv2010

Realizing high current gain PNP transistors using a novel Surface Accumulation Layer Transistor (SALTran) concept

In this paper we report a new PNP Surface Accumulation Layer Transistor (SALTran) on SOI which uses the concept of surface accumulation of holes near the emitter contact to significantly improve the current gain. Using two-dimensional simulation, we have evaluated the performance of the proposed device in detail by comparing its characteristics with those of the previously published conventional PNP lateral bipolar transistor (LBT) structure. From our simulation results it is observed that depending on the choice of the emitter doping and the emitter length, the proposed SALTran exhibits a current gain enhancement of around 20 times that of the compatible lateral bipolar transistor without deteriorating the cut-off frequency. We have discussed the reasons for the improved performance of the SALTran based on our detailed simulation results.

cond-mat.mes-hall↗
arXiv2010

Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation

For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an analytical model for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs, suitable for analog circuit simulation, is developed. We demonstrate significant current enhancement due to strain, even in short channel devices, attributed to the velocity overshoot effect. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.

cond-mat.mes-hall↗
arXiv2010

A New Strained-Silicon Channel Trench-gate Power MOSFET: Design and Analysis

In this paper, we propose a new trench power MOSFET with strained Si channel that provides lower on resistance than the conventional trench MOSFET. Using a 20% Ge mole fraction in the Si1-xGex body with a compositionally graded Si1-xGex buffer in the drift region enables us to create strain in the channel along with graded strain in the accumulation region. As a result, the proposed structure exhibits 40% enhancement in current drivability, 28% reduction in the on-resistance and 72% improvement in peak transconductance at the cost of only 12% reduction in the breakdown voltage when compared to the conventional trench gate MOSFET. Furthermore, the graded strained accumulation region supports the confinement of carriers near the trench sidewalls improving the field distribution in the mesa structure useful for a better damage immunity during inductive switching.

cond-mat.mtrl-sci↗
arXiv2010

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

In this work, we propose a new Stepped Oxide Hetero-Material Trench (SOHMT) power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving (i) a good gate control on the channel charge and (ii) a lesser gate to drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high speed switching applications. In addition, the sandwiched gate with different work function gate materials modifies the electric field profile in the channel resulting in an improved breakdown voltage. Using two-dimensional simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench gate MOSFET.

cond-mat.mtrl-sci↗
arXiv2010

New Silicon Carbide (SiC) Hetero-Junction Darlington Transistor

Basic SiC bipolar transistors have been studied in the past for their applications where high power or high temperature operation is required. However since the current gain in SiC bipolar transistors is very low and therefore, a large base drive is required in high current applications. Therefore, it is important to enhance the current gain of SiC bipolar transistors. Using two dimensional mixed mode device and circuit simulation, for the first time, we report a new Darlington transistor formed using two polytypes 3C-SiC and 4H-SiC having a very high current gain as a result of the heterojunction formation between the emitter and the base of transistor. The reasons for the improved performance are analyzed.

cond-mat.mtrl-sci↗
arXiv2010

Silicon-On-Insulator Lateral Dual Sidewall Schottky (SOI-LDSS) Concept for Improved Rectifier Performance: A Two-Dimensional Simulation Study

In this paper, we demonstrate that the performance of silicon Schottky rectifiers on SOI can be significantly improved using a Lateral Dual Sidewall Schottky (LDSS) concept. Our results based on numerical simulation show that the LDSS structure on SOI has low forward voltage drop and low reverse leakage current while its breakdown voltage is significantly larger than that of a conventional Schottky rectifier.

cond-mat.mtrl-sci↗
arXiv2010

Realizing Wide Bandgap P-SiC-emitter Lateral Heterojunction Bipolar Transistors with low collectoremitter offset voltage and high current gain - A novel proposal using numerical simulation

We report a novel method to reduce the collector-emitter offset-voltage of the wide bandgap SiC-P-emitter lateral HBTs using a dual-bandgap emitter. In our approach, the collector-emitter offset-voltage VCE(offset) is reduced drastically by eliminating the built-in potential difference between the emitter-base (EB) junction and collector-base (CB) junction by using a SiC-on-Si P-emitter. We demonstrate that the proposed dualbandgap P-emitter HBT together with the SiGe base and Schottky collector, not only has a very low VCE(offset) but also exhibits high current gain, reduced Kirk effect, excellent transient response and high cutoff frequency. We evaluated the performance of the proposed device in detail using two dimensional device simulation and a possible BiCMOS compatible fabrication procedure is also suggested.

cond-mat.mes-hall↗
arXiv2010

Compact Modeling of Parasitic Internal Fringe Capacitance Effects on the Threshold Voltage of High-K Gate Dielectric Nanoscale SOI MOSFETs

A compact model for the effect of parasitic internal fringe capacitance on threshold voltage in high-K gate dielectric SOI MOSFETs is developed. Our model includes the effects of the gate dielectric permittivity, spacer oxide permittivity, spacer width, gate length and width of MOS structure. A simple expression for parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. We demonstrate an increase in surface potential along the channel due to these charges resulting in a decrease in the threshold voltage with increase in gate dielectric permittivity. The accuracy of the results obtained using our analytical model is verified using 2-D device simulations.

cond-mat.mes-hall↗
arXiv2010

Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance

In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI LDMOS with an extended-p+ region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n+p+ junction instead of an n+p junction thus delaying the parasitic BJT action. The stepped gate structure enhances RESURF in the drift region, and minimizes the gate-drain capacitance. Based on two-dimensional simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.

cond-mat.mes-hall↗
arXiv2010

Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability: A Review

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation (CLM) and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

cond-mat.mes-hall↗
arXiv2010

Leakage Current Reduction Techniques in Poly-Si TFTs for Active Matrix Liquid Crystal Displays:A Comprehensive Study

This paper critically examines the leakage current reduction techniques for improving the performance of poly-Si TFTs used in active matrix liquid crystal displays. This is a first comprehensive study in literature on this topic. The review assesses important proposals to circumvent the leakage current problem in poly-Si TFTs and a short evaluation of strengths and weaknesses specific to each method is presented. Also, a new device structure called the Triple Gate poly-Si TFT (TG-TFT) is discussed. The key idea in the operation of this device is to make the dominant conduction mechanism in the channel to be controlled by the accumulation charge density modulation by the gate (ACMG) and not by the gate-induced grain barrier lowering (GIGBL). Using twodimensional and two-carrier device simulation, it is demonstrated that the TG-TFT exhibits a significantly diminished pseudo-subthreshold conduction leading to several orders of magnitude reduction in the OFF state leakage current when compared to a conventional poly-Si TFT. The reasons for the improved performance are explained.

cond-mat.mes-hall↗