arXiv subjects

M. Jagadesh Kumar

Publications and source records attributed to M. Jagadesh Kumar.

At least 19 recordsLinked to original sources

arXiv2014

A Pseudo 2D-analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET

In this paper, we have worked out a pseudo two dimensional (2D) analytical model for surface potential and drain current of a long channel p-type Dual Material Gate (DMG) Gate All-Around (GAA) nanowire Tunneling Field Effect Transistor (TFET). The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3D device simulator Silvaco Atlas.

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arXiv2014

Impact of gate leakage considerations in tunnel field effect transistor design

In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods for reducing the gate leakage, we show that if the gate tunneling leakage is not considered, even for these two methods, the overall TFET off-state current will be significantly underestimated. Our results demonstrate the need to carefully account for the gate leakage in the design of TFETs just as it is done for the conventional nanoscale MOSFETs.

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arXiv2014

Compact Analytical Model of Dual Material Gate Tunneling Field Effect Transistor using Interband Tunneling and Channel Transport

In this paper we have developed a two dimensional (2D) analytical model for surface potential and drain current for a long channel Dual Material Gate (DMG) Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using two-dimensional numerical simulations. In comparison to the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (ION), a better ON-state to OFF-state current (ION/IOFF) ratio and a better sub-threshold slope (SS).

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arXiv2014

Dielectric-Modulated Impact-Ionization MOS (DIMOS) Transistor as a Label-free Biosensor

In this letter, we propose a dielectric-modulated Impact-Ionization MOS (DIMOS) transistor based sensor for application in label-free detection of biomolecules. Numerous reports exist on the experimental demonstration of nanogap-embedded FET-based biosensors, but an I-MOS based biosensor has not been reported previously. The concept of a dielectric-modulated I-MOS based biosensor is presented in this letter based on TCAD simulation study. The results indicate a high sensitivity to the presence of biomolecules even at small channel lengths. In addition, a low variability of the sensitivity to the charges on the biomolecule is observed. The high sensitivity, dominance of dielectric-modulation effects and operation at even small channel lengths makes the DIMOS biosensor a promising alternative for CMOS-based sensor applications.

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arXiv2013

Doping-less Tunnel Field Effect Transistor: Design and Investigation

Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Further, fabrication of doping-less TFET does not require high-temperature doping/annealing processes and therefore, cuts down the thermal budget opening up the possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

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arXiv2013

Schottky Collector Bipolar Transistor without Impurity Doped Emitter and Base: Design and Performance

In this paper, we report an alternative approach of implementing a Schottky collector bipolar transistor without doping the ultrathin SOI film. Using different metal work function electrodes, the electrons and holes are induced in an intrinsic silicon film to create the n emitter and the p base regions, respectively. Using two-dimensional device simulation, the performance of the proposed device has been evaluated. Our results demonstrate that the charge plasma based bipolar transistor with Schottky collector exhibits a high current gain and a better cut-off frequency compared to its conventional counterpart.

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arXiv2012

Trench Gate Power MOSFET: Recent Advances and Innovations

The trench gate MOSFET has established itself as the most suitable power device for low to medium power applications by offering the lowest possible ON resistance among all MOS devices. The evolution of the trench gate power MOSFET has been discussed in this chapter, starting right from its beginnings to the recent trends. The innovations in the structural improvements to meet the requirements for an efficient operation, the progress in the fabrication technology, the characterization methods and various reliability issues have been emphasized.

cond-mat.mtrl-sci↗

arXiv2012

Bipolar Charge Plasma Transistor: A Novel Three Terminal Device

A distinctive approach for forming a lateral Bipolar Charge Plasma Transistor (BCPT) is explored using 2-D simulations. Different metal work-function electrodes are used to induce n- and p-type charge plasma layers on undoped SOI to form the emitter, base and collector regions of a lateral NPN transistor. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped lateral bipolar junction transistor with identical dimensions. Our simulation results demonstrate that the BCPT concept will help us realize a superior bipolar transistor in terms of a high current gain compared to a conventional BJT. This BCPT concept is suitable in overcoming doping issues such as dopant activation and high-thermal budgets which are serious issues in ultra thin SOI structures.

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arXiv2011

Investigation of the Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field Effect Transistor

In this paper, we propose the application of a Dual Material Gate (DMG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows a significantly improved performance. We apply the technique of DMG in a Strained Double Gate Tunnel Field Effect Transistor with a high-k gate dielectric to show an overall improvement in the characteristics of the device along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses and power supply levels to achieve significant gains in the overall device characteristics.

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arXiv2010

Estimation and Compensation of Process Induced Variations in Nanoscale Tunnel Field Effect Transistors (TFETs) for Improved Reliability

Tunnel Field Effect Transistors (TFET) have extremely low leakage current, exhibit excellent subthreshold swing and are less susceptible to short channel effects. However, TFETs do face certain special challenges, particularly with respect to the process induced variations in (i) the channel length and (ii) the thickness of the silicon thin-film and the gate oxide. This paper, for the first time, studies the impact of the above process variations on the electrical characteristics of a Double Gate Tunnel Field Effect Transistor (DGTFET). Using two dimensional device simulations, we propose the Strained Double Gate Tunnel Field Effect Transistor (SDGTFET) with high-k gate dielectric as a possible solution for effectively compensating the process induced variations in the on-current, threshold voltage and subthreshold-swing improving the reliability of the DGTFET.

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arXiv2010

Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI for VLSI applications

A novel bipolar transistor structure, namely, a SiC emitter lateral NPM Schottky collector bipolar transistor (SCBT) with a silicon-on-insulator (SOI) substrate is explored using two-dimensional (2-D) simulation. A comprehensive comparison of the proposed structure with its equivalent Si lateral NPN BJT and an SiC emitter lateral NPN HBT is presented. Based on simulation results, the authors demonstrate for the first time that the proposed SiC emitter lateral NPM transistor shows superior performance in terms of high current gain and cut-off frequency, reduced collector resistance, negligible reverse recovery time and suppressed Kirk effect over its equivalent Si lateral NPN BJT and SiC emitter lateral NPN HBT. A simple fabrication process compatible with BiCMOS technology is also discussed.

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arXiv2010

Nanoscale SOI-MOSFETs with Electrically Induced Source/Drain Extension: Novel attributes and Design considerations for Suppressed Short-channel Effects

Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.

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arXiv2010

Shielded Ohmic Contact (ShOC) Rectifier: A New Metal-Semiconductor Device with Excellent Forward and Reverse Characteristics

We report a new structure, called the Shielded Ohmic Contact (ShOC) rectifier which utilizes trenches filled with a high barrier metal to shield an Ohmic contact during the reverse bias. When the device is forward biased, the Ohmic contact conducts with a low forward drop. However, when reverse biased, the Ohmic contact is completely shielded by the high barrier Schottky contact resulting in a low reverse leakage current. Two dimensional numerical simulation is used to evaluate and explain the superior performance of the proposed ShOC rectifier.

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arXiv2010

A New High Voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) Rectifier: Theoretical Investigation and Analysis

In this paper, we report a new 4H-SiC Lateral Dual Sidewall Schottky (LDSS) rectifier on a highly doped drift layer consisting of a high-barrier sidewall Schottky contact on top of the low-barrier Schottky contact. Using two-dimensional device simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the compatible Lateral Conventional Schottky (LCS) and Lateral Trench Sidewall Schottky (LTSS) rectifiers on 4H-SiC. From our simulation results, it is observed that the proposed LDSS rectifier acts as a low-barrier LTSS rectifier under forward bias conditions and as a high-barrier LTSS rectifier under reverse bias conditions making it an ideal rectifier. The LDSS rectifier exhibits an on/off current ratio (at 1 V / -500 V) of 5.5x10e7 for an epitaxial layer doping of 1x10e17 /cm^3. Further, the proposed LDSS structure exhibits a very sharp breakdown similar to that of a PiN diode in spite of using only Schottky junctions in the structure. We have analyzed the reasons for the improved performance of the LDSS.

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arXiv2010

Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis

Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.

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arXiv2010

3D Simulation of Nanowire FETs using Quantum Models

After more than 30 years of validation of Moore's law, the CMOS technology has already entered the nanoscale (sub-100nm) regime and faces strong limitations. The nanowire transistor is one candidate which has the potential to overcome the problems caused by short channel effects in SOI MOSFETs and has gained signifi - cant attention from both device and circuit developers. In addition to the effective suppression of short channel effects due to the improved gate strength, the multi-gate NWFETs show excellent current drive and have the merit that they are compatible with conventional CMOS processes. To simulate these devices, accurate modeling and calculations based on quantum mechanics are necessary to assess their performance limits, since cross-sections of the multigate NWFETs are expected to be a few nanometers wide in their ultimate scaling. In this paper we have explored the use of ATLAS including the Bohm Quantum Potential (BQP) for simulating and studying the shortchannel behaviour of nanowire FETs.

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arXiv2010

New Schottky-gate Bipolar Mode Field Effect Transistor (SBMFET): Design and Analysis using Two-dimensional Simulation

A new Schottky-gate Bipolar Mode Field Effect Transistor (SBMFET) is proposed and verified by two-dimensional simulation. Unlike in the case of conventional BMFET, which uses deep diffused p+-regions as the gate, the proposed device uses the Schottky gate formed on the silicon planar surface for injecting minority carriers into the drift region. The SBMFET is demonstrated to have improved current gain, identical breakdown voltage and ON-voltage drop when compared to the conventional BMFET. Since the fabrication of the SBMFET is much simpler and obliterates the need for deep thermal diffusion of P+-gates, the SBMFET is expected to be of great practical importance in medium-power high-current switching applications.

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arXiv2010

Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-On-Insulator Metal-Oxide- Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect- Transistor (MOSFET) in which the front gate consists of two materials with different work functions.

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