arXiv subjects

M. Prunnila

Publications and source records attributed to M. Prunnila.

24 records · Page 2Linked to original sources

arXiv2010

Ex-situ Tunnel Junction Process Technique Characterized by Coulomb Blockade Thermometry

We investigate a wafer scale tunnel junction fabrication method, where a plasma etched via through a dielectric layer covering bottom Al electrode defines the tunnel junction area. The ex-situ tunnel barrier is formed by oxidation of the bottom electrode in the junction area. Room temperature resistance mapping over a 150 mm wafer give local deviation values of the tunnel junction resistance that fall below 7.5 % with an average of 1.3 %. The deviation is further investigated by sub-1 K measurements of a device, which has one tunnel junction connected to four arrays consisting of N junctions (N = 41, junction diameter 700 nm). The differential conductance is measured in single-junction and array Coulomb blockade thermometer operation modes. By fitting the experimental data to the theoretical models we found an upper limit for the local tunnel junction resistance deviation of ~5 % for the array of 2N+1 junctions. This value is of the same order as the minimum detectable deviation defined by the accuracy of our experimental setup.

cond-mat.mtrl-sci↗

arXiv2008

Electrons and holes in Si quantum well: a room-temperature transport and drag resistance study

We investigate carrier transport in a single 22 nm-thick double-gated Si quantum well device, which has independent contacts to electrons and holes. Conductance, Hall density and Hall mobility are mapped in a broad double-gate voltage window. When the gate voltage asymmetry is not too large only either electrons or holes occupy the Si well and the Hall mobility shows the fingerprints of volume inversion/accumulation. At strongly asymmetric double-gate voltage an electric field induced electron-hole (EH) bi-layer is formed inside the well. The EH drag resistance R_{he} is explored at balanced carrier densities: R_{he} decreases monotonically from 860 to 37 Ohms when the electron and hole density is varied between ~0.4-1.7x10^{16} m^{-2}.

cond-mat.mtrl-sci↗

arXiv2006

Double Gate Bias Dependency of Low Temperature Conductivity of SiO2-Si-SiO2 Quantum Wells

The gate bias dependency of conductivity is examined in two Si quantum wells with well thickness tw = 7 nm and tw = 14 nm. The conductivity of the thinner device behaves smoothly whereas the thicker device shows strong non-monotonic features as a function of gate voltages. We show that a strong minimum in conductivity occurs close to the threshold of second sub-band. Another minimum is seen at high electron density at symmetric well potential. This feature is addressed to sub-band wave function delocalization in the quantization direction.

cond-mat.other↗

arXiv2006

Energy Transport between Hole Gas and Crystal Lattice in Diluted Magnetic Semiconductor

The temperature dependent energy transfer rate between charge carriers and lattice has been experimentally investigated in ferromagnetic semiconductors. Studied 100 nm thick low-temperature MBE grown Mn_{x}Ga_{1-x}As samples had manganese concentrations x=3.7 % and 4.0 %. Curie temperatures estimated from temperatures of peak resistivities were 60 K and 62 K, respectively.

cond-mat.mtrl-sci↗

arXiv2005

Intervalley-Scattering Induced Electron-Phonon Energy Relaxation in Many-Valley Semiconductors at Low Temperatures

We report on the effect of elastic intervalley scattering on the energy transport between electrons and phonons in many-valley semiconductors. We derive a general expression for the electron-phonon energy flow rate at the limit where elastic intervalley scattering dominates over diffusion. Electron heating experiments on heavily doped n-type Si samples with electron concentration in the range $3.5-16.0\times 10^{25}$ m$^{-3}$ are performed at sub-1 K temperatures. We find a good agreement between the theory and the experiment.

cond-mat.dis-nn↗

arXiv2005

Electron Mobility and Magneto Transport Study of Ultra-Thin Channel Double-Gate Si MOSFETs

We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range 7-17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/Vs, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing.

cond-mat.mtrl-sci↗