arXiv subjects

Matteo Lupi

Publications and source records attributed to Matteo Lupi.

4 recordsLinked to original sources

arXiv2026

Challenges in the verification of MOSAIX ASIC for ALICE ITS3

The MOSAIX is a wafer-scale, full-functionality prototype ASIC for the ALICE Inner Tracking System (ITS3) upgrade, implemented in $65\,\text{nm}$ stitching technology. It integrates 144 independently powered pixel matrices, eight $10\,\text{Gb/s}$ serializers, and on-chip data and power distribution, making full-chip verification highly resource-intensive (over $80\,\text{GB}$ of memory and 192,000 tests). Verification also targets a sophisticated power-up sequence and radiation conditions of $10^{6}$\ particles $s^{-1} cm^{-2}$ and $4\,\text{kGy}$ TID. This work presents a UVM-based verification strategy that identified 260 design errors and summarizes key lessons from ASIC sign-off.

physics.ins-det↗

arXiv2025

Characterisation of the first wafer-scale prototype for the ALICE ITS3 upgrade: the monolithic stitched sensor (MOSS)

This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026-2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 $\times$ 25.9 cm, thinned to 50 $μ$m. The chip architecture, in-pixel front-end, laboratory and in-beam characterisation, susceptibility to single-event effects, and series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.

physics.ins-det↗

arXiv2025

Introducing GeoHEAT: Georadar-aided High-resolution Exploration for Advancing geoThermal energy usage

We present a novel geothermal exploration approach that integrates innovations at three spatial scale. At the regional scale (~100 km) we create LCOE heat maps using a techno-economic and metamodel analysis. This allows us to choose several potential sites to perform a reservoir scale (~10 km) assessment with passive seismics and gravity. By integrating the latter with probabilistic geological and geomechanical modeling we propose locations to drill exploration boreholes. Then follows a high-resolution borehole characterization incorporating various analyses, the central one being a georadar probe that allows to illuminate permeable structures. Within this project, we also design and build a geothermal grade georadar. Here, we present the approach and result from the application of our methodology to the Swiss canton of Thurgau, with the purpose of large-scale geothermal exploration.

physics.geo-ph↗

arXiv2020

Remote Configuration of the ProASIC3 on the ALICE Inner Tracking System Readout Unit

A Large Ion Collider Experiment (ALICE) is one of the four major experiments conducted at the CERN Large Hadron Collider (LHC). The ALICE detector is currently undergoing an upgrade for the upcoming Run 3 at the LHC. The new Inner Tracking System (ITS) sub-detector is part of this upgrade. The front-end electronics of the ITS is composed by 192 Readout Units, installed in a radiation environment. Single Event Upsets (SEUs) in the SRAM-based Xilinx Kintex Ultrascale FPGAs used in the ITS readout represent a real concern. To clear SEUs affecting the Kintex configuration memory, a secondary Flash-based Microsemi ProASIC3E (PA3) FPGA is used. This device configures and continuously scrubs the Xilinx FPGA while data-taking is ongoing, which avoids accumulation of SEUs. The communication path to the RUs is via the radiation hard Gigabit Transceiver (GBT) system on 100 m long optical links. The PA3 is reachable via the GBT Slow Control Adapter (GBT-SCA) ASIC using a dedicated JTAG bus driving channel. During the course of Run 3, it is foreseeable that the FPGA design of the PA3 will require upgrades to correct possible issues and add new functionality. It is therefore mandatory that the PA3 itself can be configured remotely, for which a dedicated software tool is needed. This paper presents the design and implementation of the distributed tools to re-configure remotely the PA3 FPGAs.

physics.ins-det↗