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Michiel van Setten

Publications and source records attributed to Michiel van Setten.

3 recordsLinked to original sources

Subthreshold Swing Behavior in Amorphous Indium-Gallium-Zinc-Oxide Transistors from Room to Cryogenic Temperatures

While cryogenic-temperature subthreshold swing (SS) in crystalline semiconductors has been widely studied, a careful study on the temperature-dependent SS in amorphous oxide semiconductors remains lacking. In this paper, a comprehensive analysis of the SS in thin-film transistors with an amorphous indium gallium zinc oxide (IGZO) channel at temperatures from 300 K down to 4 K is presented. Main observations include: 1) At room temperature (300 K), the devices exhibit a SS of 61 mV/dec, and a low interface trap density (<1011 cm-2), among the best reported values for IGZO devices. 2) A SS saturation around 40 mV/dec is observed between 200 K and 100 K. It is well explained by the electron transport via band tail states with exponential decay (Wt) of 13 meV. 3) At deep-cryogenic temperature, SS increase significantly exceeding 200 mV/dec at 4 K. Such high SS values are actually limited by the measurement current range, confirmed by Id-Vg simulations based on the variable range hopping (VRH) model. This work not only elucidates the SS behavior in amorphous IGZO devices but also provides a deep understanding of the physical mechanisms of electron transport in amorphous semiconductors.

cond-mat.mtrl-sci

The impact of process steps on nearly ideal subthreshold slope in 300-mm compatible InGaZnO TFT

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) ~ 60 mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T = 4 K - 300 K) and multi-frequency (f = 1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

physics.app-ph

Sub-40mV Sigma-VTH IGZO nFETs in 300mm Fab

Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively leveraging 300mm fab processing. While the passivation of oxygen vacancies in IGZO is challenging with an integration of front side gate, a scaled back gated flow has been optimized by multiplying design of experiments around contacts and material engineering. We then successfully demonstrated sub-40mV $\sigma$(VTH_ON) in scaled IGZO nFETs. Regarding the performance and the VTH_ON control, a new IGZO phase is also reported. A model of dopants location is proposed to better explain the experimental results reported in literature.

cond-mat.mtrl-sci