arXiv subjects

Olga Krestinskaya

Publications and source records attributed to Olga Krestinskaya.

29 records · Page 2Linked to original sources

arXiv2018

Real-time Analog Pixel-to-pixel Dynamic Frame Differencing with Memristive Sensing Circuits

In this paper, we propose an analog pixel differencing circuit for differentiating pixels between frames directly from CMOS pixels. The analog information processing at sensor is a topic of growing appeal to develop edge AI devices. The proposed circuit is integrated into a pixel-parallel and pixel-column architectures. The proposed system is design using TSMC $180nm$ CMOS technology. The power dissipation of the proposed circuit is $96.64mW$, and on-chip ares is $531.66 μm^2$. The architectures are tested for moving object detection application.

cs.ET↗

arXiv2018

Approximate Probabilistic Neural Networks with Gated Threshold Logic

Probabilistic Neural Network (PNN) is a feed-forward artificial neural network developed for solving classification problems. This paper proposes a hardware implementation of an approximated PNN (APNN) algorithm in which the conventional exponential function of the PNN is replaced with gated threshold logic. The weights of the PNN are approximated using a memristive crossbar architecture. In particular, the proposed algorithm performs normalization of the training weights, and quantization into 16 levels which significantly reduces the complexity of the circuit.

cs.ET↗

arXiv2018

Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing

The memristive crossbar aims to implement analog weighted neural network, however, the realistic implementation of such crossbar arrays is not possible due to limited switching states of memristive devices. In this work, we propose the design of an analog deep neural network with binary weight update through backpropagation algorithm using binary state memristive devices. We show that such networks can be successfully used for image processing task and has the advantage of lower power consumption and small on-chip area in comparison with digital counterparts. The proposed network was benchmarked for MNIST handwritten digits recognition achieving an accuracy of approximately 90%.

cs.ET↗

arXiv2018

Design of CMOS-memristor Circuits for LSTM architecture

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.

cs.ET↗

arXiv2018

Effects of Memristors on Fully Differential Transimpedance Amplifier Performance

The progress of the Internet of Things(IoT) technologies and applications requires the efficient low power circuits and architectures to maintain and improve the performance of the increasingly growing data processing systems. Memristive circuits and substitution of energy-consuming devices with memristors is a promising solution to reduce on-chip area and power dissipation of the architectures. In this paper, we proposed a CMOS-memristive fully differential transimpedance amplifier and assess the impact of memristors on the amplifier performance. The fully differential amplifiers were simulated using 180nm CMOS technology and have 5.3-23MHz bandwidths and 2.3-5.7k$Ω$ transimpedance gains with a 1pF load. We compare the memristor based amplifier with conventional architecture. The gain, frequency response, linear range, power consumption, area, total harmonic distortion and performance variations with temperature are reported.

cs.ET↗

arXiv2018

Hierarchical Temporal Memory using Memristor Networks: A Survey

This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed.

cs.AR↗

arXiv2018

Feature extraction without learning in an analog Spatial Pooler memristive-CMOS circuit design of Hierarchical Temporal Memory

Hierarchical Temporal Memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary weights and random weight assignment in the initialization stage of the HTM. We propose the alternative deterministic method for the HTM initialization stage, which connects the HTM weights to the input data and preserves natural sparsity of the input information. Further, we introduce the hardware implementation of the deterministic approach and compare it to the traditional HTM and existing hardware implementation. We test the proposed approach on the face recognition problem and show that it outperforms the conventional HTM approach.

cs.ET↗

arXiv2018

Facial emotion recognition using min-max similarity classifier

Recognition of human emotions from the imaging templates is useful in a wide variety of human-computer interaction and intelligent systems applications. However, the automatic recognition of facial expressions using image template matching techniques suffer from the natural variability with facial features and recording conditions. In spite of the progress achieved in facial emotion recognition in recent years, the effective and computationally simple feature selection and classification technique for emotion recognition is still an open problem. In this paper, we propose an efficient and straightforward facial emotion recognition algorithm to reduce the problem of inter-class pixel mismatch during classification. The proposed method includes the application of pixel normalization to remove intensity offsets followed-up with a Min-Max metric in a nearest neighbor classifier that is capable of suppressing feature outliers. The results indicate an improvement of recognition performance from 92.85% to 98.57% for the proposed Min-Max classification method when tested on JAFFE database. The proposed emotion recognition technique outperforms the existing template matching methods.

cs.CV↗

arXiv2017

Neuromorphic adaptive edge-preserving denoising filter

In this paper, we present on-sensor neuromorphic vision hardware implementation of denoising spatial filter. The mean or median spatial filters with fixed window shape are known for its denoising ability, however, have the drawback of blurring the object edges. The effect of blurring increases with an increase in window size. To preserve the edge information, we propose an adaptive spatial filter that uses neuron's ability to detect similar pixels and calculates the mean. The analog input differences of neighborhood pixels are converted to the chain of pulses with voltage controlled oscillator and applied as neuron input. When the input pulses charge the neuron to equal or greater level than its threshold, the neuron will fire, and pixels are identified as similar. The sequence of the neuron's responses for pixels is stored in the serial-in-parallel-out shift register. The outputs of shift registers are used as input to the selector switches of an averaging circuit making this an adaptive mean operation resulting in an edge preserving mean filter. System level simulation of the hardware is conducted using 150 images from Caltech database with added Gaussian noise to test the robustness of edge-preserving and denoising ability of the proposed filter. Threshold values of the hardware neuron were adjusted so that the proposed edge-preserving spatial filter achieves optimal performance in terms of PSNR and MSE, and these results outperforms that of the conventional mean and median filters.

eess.IV↗

arXiv2017

On-chip Face Recognition System Design with Memristive Hierarchical Temporal Memory

Hierarchical Temporal Memory is a new machine learning algorithm intended to mimic the working principle of neocortex, part of the human brain, which is responsible for learning, classification, and making predictions. Although many works illustrate its effectiveness as a software algorithm, hardware design for HTM remains an open research problem. Hence, this work proposes an architecture for HTM Spatial Pooler and Temporal Memory with learning mechanism, which creates a single image for each class based on important and unimportant features of all images in the training set. In turn, the reduction in the number of templates within database reduces the memory requirements and increases the processing speed. Moreover, face recognition analysis indicates that for a large number of training images, the proposed design provides higher accuracy results (83.5\%) compared to only Spatial Pooler design presented in the previous works.

cs.ET↗

arXiv2015

Memristor Load Current Mirror Circuit

Simple current mirrors with semiconductor resistive loads suffer from large on-chip area, leakage currents and thermal effects. In this paper, we report the feasibility of using memristive loads as a replacement of semiconductor resistors in simplistic current mirror configuration. We report power, area and total harmonic distribution, and report the corner conditions on resistance tolerances.

cs.ET↗