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Pariasadat Musavigharavi

Publications and source records attributed to Pariasadat Musavigharavi.

7 recordsLinked to original sources
arXiv2024

Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes

The deluge of sensors and data generating devices has driven a paradigm shift in modern computing from arithmetic-logic centric to data-centric processing. Data-centric processing require innovations at device level to enable novel compute-in-memory (CIM) operations. A key challenge in construction of CIM architectures is the conflicting trade-off between the performance and their flexibility for various essential data operations. Here, we present a transistor-free CIM architecture that permits storage, search and neural network operations on sub-50nm thick Aluminum Scandium Nitride ferroelectric diodes (FeDs). Our circuit designs and devices can be directly integrated on top of Silicon microprocessors in a scalable process. By leveraging the field-programmability, non-volatility and non-linearity of FeDs, search operations are demonstrated with a cell footprint < 0.12 um2 when projected onto 45-nm node technology. We further demonstrate neural network operations with 4-bit operation using FeDs. Our results highlight FeDs as candidates for efficient and multifunctional CIM platforms.

physics.app-ph↗
arXiv2024

Multi-State, Ultra-thin, BEOL-Compatible AlScN Ferroelectric Diodes

The growth in data generation necessitates efficient data processing technologies to address the von Neumann bottleneck in conventional computer architecture. Memory-driven computing, which integrates non-volatile memory (NVM) devices in a 3D stack, is gaining attention, with CMOS back-end-of-line (BEOL) compatible ferroelectric (FE) diodes being ideal due to their two-terminal design and inherently selector-free nature, facilitating high-density crossbar arrays. Here, we demonstrate BEOL-compatible, high-performance FE-diodes scaled to 5, 10, and 20 nm FE Al0.72Sc0.28N/Al0.64Sc0.36N films. Through interlayer (IL) engineering, we show substantial improvements in the ON/OFF ratios (>166 times) and rectification ratios (>176 times) in these scaled devices. The superlative characteristics also enables 5-bit multi-state operation with a stable retention. We also experimentally and theoretically demonstrate the counterintuitive result that the inclusion of an IL can lead to a decrease in the ferroelectric switching voltage of the device. An in-depth analysis into the device transport mechanisms is performed, and our compact model aligns seamlessly with the experimental results. Our results suggest the possibility of using scaled AlxSc1-xN FE-diodes for high performance, low-power, embedded NVM.

cond-mat.mtrl-sci↗
arXiv2023

Non-Volatile Control of Valley Polarized Emission in 2D WSe2-AlScN Heterostructures

Achieving robust and electrically controlled valley polarization in monolayer transition metal dichalcogenides (ML-TMDs) is a frontier challenge for realistic valleytronic applications. Theoretical investigations show that integration of 2D materials with ferroelectrics is a promising strategy; however, its experimental demonstration has remained elusive. Here, we fabricate ferroelectric field-effect transistors using a ML-WSe2 channel and a AlScN ferroelectric dielectric, and experimentally demonstrate efficient tuning as well as non-volatile control of valley polarization. We measured a large array of transistors and obtained a maximum valley polarization of ~27% at 80 K with stable retention up to 5400 secs. The enhancement in the valley polarization was ascribed to the efficient exciton-to-trion (X-T) conversion and its coupling with an out-of-plane electric field, viz. the quantum-confined Stark effect. This changes the valley depolarization pathway from strong exchange interactions to slow spin-flip intervalley scattering. Our research demonstrates a promising approach for achieving non-volatile control over valley polarization and suggests new design principles for practical valleytronic devices.

cond-mat.mes-hall↗
arXiv2023

Scalable and Stable Ferroelectric Non-Volatile Memory at > 500 $^\circ$C

Non-volatile memory (NVM) devices that reliably operate at temperatures above 300 $^\circ$C are currently non-existent and remains a critically unmet challenge in the development of high-temperature (T) resilient electronics, necessary for many emerging, complex computing and sensing in harsh environments. Ferroelectric Al$_x$Sc$_{1-x}$N exhibits strong potential for utilization in NVM devices operating at very high temperatures (> 500 $^\circ$C) given its stable and high remnant polarization (PR) above 100 $μ$C/cm$^2$ with demonstrated ferroelectric transition temperature (TC) > 1000 $^\circ$C. Here, we demonstrate an Al$_{0.68}$Sc$_{0.32}$N ferroelectric diode based NVM device that can reliably operate with clear ferroelectric switching up to 600 $^\circ$C with distinguishable On and Off states. The coercive field (EC) from the Pulsed I-V measurements is found to be -5.84 (EC-) and +5.98 (EC+) (+/- 0.1) MV/cm at room temperature (RT) and found to decrease with increasing temperature up to 600 $^\circ$C. The devices exhibit high remnant polarizations (> 100 $μ$C/cm$^2$) which are stable at high temperatures. At 500 $^\circ$C, our devices show 1 million read cycles and stable On-Off ratio above 1 for > 6 hours. Finally, the operating voltages of our AlScN ferrodiodes are < 15 V at 600 $^\circ$C which is well matched and compatible with Silicon Carbide (SiC) based high temperature logic technology, thereby making our demonstration a major step towards commercialization of NVM integrated high-T computers.

physics.app-ph↗
arXiv2022

Scalable CMOS-BEOL compatible AlScN/2D Channel FE-FETs

Intimate integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrently with enhanced energy efficiency in big-data applications such as artificial intelligence. Despite decades of efforts, reliable, compact, energy efficient and scalable memory devices are elusive. Ferroelectric Field Effect Transistors (FE-FETs) are a promising candidate but their scalability and performance in a back-end-of-line (BEOL) process remain unattained. Here, we present scalable BEOL compatible FE-FETs using two-dimensional (2D) MoS2 channel and AlScN ferroelectric dielectric. We have fabricated a large array of FE-FETs with memory windows larger than 7.8 V, ON/OFF ratios of greater than 10^7, and ON current density greater than 250 uA/um, all at ~80 nm channel lengths. Our devices show stable retention up to 20000 secs and endurance up to 20000 cycles in addition to 4-bit pulse programmable memory features thereby opening a path towards scalable 3D hetero-integration of 2D semiconductor memory with Si CMOS logic.

physics.app-ph↗
arXiv2020

Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor

In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memory (NVM) technology. Over the past two decades, advances in oxide FE materials have rejuvenated the field of ferroelectrics and made FE random access memories (FE-RAM) a commercial reality. Despite these advances, commercial FE-RAM based on lead zirconium titanate (PZT) has stalled at the 130 nm due to process challenges.The recent discovery of scandium doped aluminum nitride (AlScN) as a CMOS compatible ferroelectric presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approx. 350 C). This temperature is compatible with CMOS back end of line processes. Here, we present a FE-FET device composed of an AlScN FE dielectric layer integrated with a channel layer of a van der Waals two-dimensional (2D) semiconductor, MoS2. Our devices show an ON/OFF ratio ~ 10^6, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable, two-state memory retention for up to 10^4 seconds. Our simulations and experimental results suggest that the combination of AlScN and 2D semiconductors is nearly ideal for low power FE-FET memory. These results demonstrate a new approach in embedded memory and in-memory computing, and could even lead to effective neuromorphic computing architectures.

physics.app-ph↗