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Peter Orel

Publications and source records attributed to Peter Orel.

At least 19 recordsLinked to original sources

VERITAS 2.3.1: Optimisation and Characterisation of the Enhanced Readout ASIC for the NewAthena Wide Field Imager

VERITAS 2.3.1 is the next iteration of the VErsatile Readout based on Integrated Trapezoidal Analogue Shapers (VERITAS) integrated circuit (IC) architecture for high-speed, low-noise readout of DEPleted Field Effect Transistor (DEPFET) detectors in the Wide Field Imager (WFI) on ESA's NewAthena X-ray satellite. Building on VERITAS 2.3, which demonstrated a short processing time of 2.5 us per readout and a system noise target of about 3 e- ENC RMS, the VERITAS 2.3.1 revision has been improved with additional features and targeted optimisations of existing analogue and digital blocks, alongside refined layout routing to reduce parasitic effects, to improve transient behavior, cross talk, manufacturability, and reliability while preserving the proven VERITAS architecture. The functionality and performance of VERITAS 2.3.1 was characterised in two steps. First by using a dedicated application specific integrated circuit (ASIC) only test setup. Second, a full scale module test setup is used, with integrated DEPFET sensors and readout electronics, under vacuum and at mission like temperatures. This paper presents the design updates and implementation details of the VERITAS 2.3.1, compares its measured performance to that of VERITAS 2.3, and discusses the impact of the added features, block-level optimisations, and routing improvements on overall system performance.

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Fast, low noise, megapixel detector and readout systems for future X-ray astronomy missions

Next-generation strategic X-ray astronomy missions will require the simultaneous achievement of high angular resolution, large effective collecting area, and wide-field imaging with large-format focal plane detectors. Realizing the associated science objectives--ranging from precision measurements of bright point sources to the detection and characterization of faint diffuse emission-places stringent and, in some cases, competing requirements on detector performance. In particular, high frame rates are necessary to mitigate photon pile-up in observations of bright sources and to reduce contamination from particle-induced background in measurements of low surface brightness structures. At the same time, these instruments must preserve excellent soft X-ray response, which places tight constraints on read noise and on the fidelity of event characterization. State-of-the-art X-ray charge-coupled devices (CCDs) approach many of the key performance metrics required for these missions, but readout speed remains a primary limitation. Addressing this gap requires readout architectures that scale to high channel count, sustain high pixel throughput, and preserve the low-noise characteristics needed for soft X-ray sensitivity.

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High-speed, low-noise, multi-megapixel CCDs for next generation X-ray observatories

Next generation X-ray observatories require fast, low-noise, low-power, multi-megapixel imaging spectrometers. To meet these demands, the X-ray Astronomy and Observational Cosmology (XOC) Group at Stanford, in partnership with the MIT Kavli Institute and MIT Lincoln Laboratory (MIT-LL), is developing multi-channel X-ray charge-coupled devices (CCDs) and fast readout architectures. We report the energy resolution and noise performance achieved with a full-scale (1440x1440-pixel), 16-channel, front-illuminated MIT-LL CCD detector developed for the Advanced X-ray Imaging Satellite (AXIS) concept, the CCID-100, read out using two Multi-Channel Readout Chip (MCRC) V1 application-specific integrated circuit (ASIC) chips in the new Stanford CCID-100 test setup. We describe an automated method for bias optimization on each CCD channel, and integrated debugging features of the front-end ASIC and readout system. The demonstrated performance confirms that these systems can meet the speed and noise requirements of future strategic X-ray missions.

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Advancing X-Ray Camera Front-End Electronics Architecture through the AXIS-TAP Technology Platform

Advancing time-domain soft X-ray astronomy demands focal plane readout electronics capable of high-speed digitization with low noise while maintaining spectral fidelity across multiple detector channels. The Advanced X-ray Imaging Satellite (AXIS), a NASA Probe-class mission concept, provided the driving requirements and heritage for developing a generalized high-speed (>=5 fps) camera Front-End Electronics (FEE) architecture applicable to future soft X-ray missions. The FEE architecture defines a modular, dual-box redundant configuration to operate a focal plane of four 16-channel CCDs, with functional partitioning for power distribution, thermal management, mechanism control, and image data acquisition and transmission to the spacecraft. To validate the core signal chain architecture, particularly the analog-to-digital conversion, FPGA-based processing, and Ethernet data transmission, a dedicated technology demonstrator, AXIS-TAP (ADC Testing and Acquisition Platform), has been designed and is currently in fabrication. AXIS-TAP employs commercial equivalents of radiation-tolerant components (FPGA, ADCs, Ethernet PHY) and interfaces directly with the STA Archon benchtop readout system, enabling simultaneous image acquisition from both systems to validate that the flight-like architecture achieves equivalent or superior noise performance. This paper presents the FEE architectural framework, the AXIS-TAP demonstrator design, and the design principles that enable scalability to future soft X-ray missions with similar detector requirements. Performance validation results will be reported upon completion of AXIS-TAP system integration and testing.

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Output-Stage Design Optimization for High-Sensitivity SiSeRO CCDs and SiSeRO Active Pixel Sensors

The Single electron Sensitive Read Out (SiSeRO) technology is a new device class designed to support the needs of future X-ray and optical astronomical telescopes that will require fast, low-noise, megapixel spectro-imagers. Developed at MIT Lincoln Laboratory, in collaboration with Stanford University and MIT, the first generation SiSeRO-CCD (charge-coupled device) prototypes achieved a charge/current conversion gain of 700$-$800 pA per electron, an equivalent noise charge (ENC) of around 3.5 electrons root mean square (RMS), and a full width half maximum (FWHM) energy resolution of approximately 130 eV at 5.9 keV at a readout speed of 625 kpix/s. Utilizing Repetitive Non-Destructive Readout (RNDR), these same devices also demonstrated sub-electron noise performance (ENC$<$0.5 electrons RMS) at a readout speed of 10 kpix/s. We present the results of device simulations for next-generation SiSeRO CCD output stages that optimize the sensing transistor and its internal gate geometry to enhance noise and speed performance. Further, the goal is to develop a SiSeRO active pixel sensor (APS) that combines the proven X-ray performance of CCDs with the architectural advantages of an APS. Enabling this requires substantial design updates, for example, incorporating two SiSeRO amplifiers side by side on each pixel and shuffling the charge between them to support RNDR. We discuss our device simulation framework and design parameter optimization in the first-generation SiSeRO devices.

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Fast, low-noise CCD systems for future strategic X-ray missions

Future strategic X-ray missions, such as those targeted by the Great Observatories Maturation Program (GOMaP), require fast, low-noise X-ray imaging spectrometers. To achieve the speed and noise capabilities required by such programs, our Stanford team, in collaboration with the MIT Kavli Institute (MKI) and MIT Lincoln Laboratory (MIT-LL), is developing enhanced X-ray charge-coupled devices (CCDs) and readout systems that leverage tailored application-specific integrated circuits (ASICs). Here, we report the energy resolution and noise performance achieved using some of the latest MIT-LL CCDs in conjunction with Stanford-developed Multi-Channel Readout Chip (MCRC) ASICs. Additionally, we present a new sampling method for simultaneous optimization of the output gate (OG), reset gate (RG), and reset drain (RD) biases which, in combination with new integrated fast summing well (SW) and RG clock operation modes, enables the data rates and noise required for future X-ray telescopes. Finally, we present noise power spectral density (PSD) and waveform analysis methods and posit a physical model for characterizing and understanding output stage noise behavior.

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The High-Speed FPGA Readout System for the Advanced X-ray Imaging Satellite (AXIS)

The Advanced X-ray Imaging Satellite (AXIS) is a Probe-class mission concept designed to deliver arcsecond spatial resolution, high-sensitivity spectral imaging across the 0.3-10 keV band. The X-ray Astronomy and Observational Cosmology (XOC) Group at Stanford, in collaboration with the MIT Kavli Institute (MKI) and MIT Lincoln Laboratory (MIT-LL), is developing the AXIS X-ray camera, including both the detector and the front-end readout electronics required to meet the mission's demanding performance goals. The telescope's focal plane detector consists of four 1440x1440 pixel charge-coupled devices (CCDs) developed by MIT-LL, each featuring 16 parallel output channels. These outputs are amplified by a high-speed, low-power, low-noise application-specific integrated circuit (ASIC) - the Multi-Channel Readout Chip (MCRC) - developed at Stanford. Following amplification, the analog signals are digitized and processed to construct a pixel array, prior to event detection. Here, we present the field-programmable gate array (FPGA) architecture developed to enable high-speed, parallelized readout of these CCD channels. The FPGA samples 16 analog-to-digital converter (ADC) channels at 50 MHz, performs preprocessing of pixel data, which is then streamed via User Datagram Protocol (UDP) over a 1 Gb Ethernet link to the back-end system for event reconstruction. Our design demonstrates the goal readout performance for AXIS (20 frames per second) and provides a framework for future high-throughput X-ray observatories.

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RNDR noise modeling in first-generation Single electron Sensitive Readout (SiSeRO) devices

Flagship observatories require single-photon detectors with ultra-fast readout, sub-electron noise performance, and scalable large-format architectures. The X-ray Astronomy and Observational Cosmology group at Stanford, in collaboration with the MIT Kavli Institute and MIT Lincoln Laboratory, is developing readout technologies for next-generation detectors. Prototypes employing Single-electron Sensitive Readout (SiSeRO) amplifiers demonstrate excellent read noise and spectral performance using repetitive non-destructive readout (RNDR), achieving 0.5 e$^-$ noise in under 57 cycles. We have modeled noise for longer RNDR cycles, exploring probabilistic mechanisms such as thermal leakage and impact ionization. Here we present our model results, including statistical limits on dark current-like signals. Maturation of SiSeRO technology will improve detector performance at soft X-ray energies, addressing technology gaps for future X-ray and UV/visible/near-IR observatories.

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First results for second generation SiSeRO CCD devices

The Astro2020 Decadal recommended the development of a suite of next generation astronomical observatories spanning the X-ray to near-IR spectrum. These programs require fast, extremely low noise detectors to fulfill their science goals. To address this technology gap, Stanford X-ray Astronomy and Observational Cosmology (XOC) group, MIT Lincoln Laboratory (MIT-LL), and MIT Kavli Institute (MKI) are advancing Single electron Sensitive Read Out (SiSeRO), a multiband detector technology capable of achieving substantially sub-electron noise via Repetitive Non-Destructive Readout (RNDR). We present initial results for our second generation SiSeRO CCDs. We also discuss our test bed, including a readout electronics system capable of accommodating all second-generation SiSeRO CCD variants utilizing the XOC-designed Multi-Channel Readout Chip (MCRC) ASIC.

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The high-speed X-ray camera on AXIS: design and performance updates

AXIS, a Probe mission concept now in a Phase A study, will provide transformative studies of high-energy astrophysical phenomena thanks to its high-resolution X-ray spectral imaging. These capabilities are enabled by improvements to the mirror design that greatly increase the X-ray throughput per unit mass; and to the detector system, which operates more than an order of magnitude faster than heritage instruments while maintaining excellent spectral performance. We present updates to the design of the AXIS High-Speed Camera, a collaborative effort by MIT, Stanford University, the Pennsylvania State University, and the Southwest Research Institute. The camera employs large-format MIT Lincoln Laboratory CCDs that feature multiple high-speed, low-noise output amplifiers and an advanced single-layer polysilicon gate structure for fast, low-power clock transfers. A first lot of prototype CCID100 CCDs has completed fabrication and will soon begin X-ray performance testing. The CCDs are paired with high-speed, low-noise ASIC readout chips designed by Stanford to provide better performance than conventional discrete solutions at a fraction of the power consumption and footprint. Complementary Front-End Electronics employ state-of-the-art digital video waveform capture and advanced signal processing to further deliver low noise at high speed. The Back-End Electronics provide high-speed identification of candidate X-ray events and transient monitoring that relays fast alerts of changing sources to the community. We highlight updates to our parallel X-ray performance test facilities at MIT and Stanford, and review the current performance of the CCD and ASIC technology from testing of prototype devices. These measurements achieve excellent spectral response at the required readout rate, demonstrating that we will meet mission requirements and enable AXIS to achieve world-class science.

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Development and testing of integrated readout electronics for next generation SiSeRO (Single electron Sensitive Read Out) devices

The first generation of Single electron Sensitive Read Out (SiSeRO) amplifiers, employed as on-chip charge detectors for charge-coupled devices (CCDs) have demonstrated excellent noise and spectral performance: a responsivity of around 800 pA per electron, an equivalent noise charge (ENC) of 3.2 electrons root mean square (RMS), and a full width half maximum (FWHM) energy resolution of 130 eV at 5.9 keV for a readout speed of 625 Kpixel/s. Repetitive Non Destructive Readout (RNDR) has also been demonstrated with these devices, achieving an improved ENC performance of 0.36 electrons RMS after 200 RNDR cycles. In order to mature this technology further, Stanford University, in collaboration with MIT Kavli Institute and MIT Lincoln Laboratory, are developing new SiSeRO detectors with improved geometries that should enable greater responsivity and improved noise performance. These include CCD devices employing arrays of SiSeRO amplifiers to optimize high speed, low noise RNDR readout and a proof-of-concept SiSeRO active pixel sensor (APS). To read out these devices, our team has developed a compact, 8-channel, fast, low noise, low power application specific integrated circuit (ASIC) denoted the Multi-Channel Readout Chip (MCRC) that includes an experimental drain current readout mode intended for SiSeRO devices. In this paper, we present results from the first tests of SiSeRO CCD devices operating with MCRC readout, and our designs for next generation SiSeRO devices.

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Fast, low noise CCD systems for future strategic x-ray missions

Future strategic X-ray missions, such as the Advanced X-ray Imaging Satellite (AXIS) and those targeted by the Great Observatories Maturation Program (GOMaP), require fast, low-noise X-ray imaging spectrometers. To achieve the speed and noise capabilities required by such programs, the X-ray Astronomy and Observational Cosmology (XOC) Group at Stanford, in collaboration with the MIT Kavli Institute (MKI) and MIT Lincoln Laboratory (MIT-LL), is developing readout systems that leverage the high speed, low noise, and low power consumption of application-specific integrated circuit (ASIC) devices. Here, we report the energy resolution and noise performance achieved using MIT-LL AXIS prototype charge-coupled device (CCD) detectors in conjunction with Stanford-developed Multi-Channel Readout Chip (MCRC) ASICs. Additionally, we present a new sampling method for simultaneous optimization of the output gate (OG), reset gate (RG), and reset drain (RD) biases which, in combination with new integrated fast summing well (SW) and RG clock operation modes, enables the data rates required of future X-ray telescopes.

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Design, development, and commissioning of a flexible test setup for the AXIS prototype detector

The Advanced X-ray Imaging Satellite (AXIS) is one of two candidate mission concepts selected for Phase-A study for the new NASA Astrophysics Probe Explorer (APEX) mission class, with a planned launch in 2032. The X-ray camera for AXIS is under joint development by the X-ray Astronomy and Observational Cosmology (XOC) Group at Stanford, the MIT Kavli Institute (MKI), and MIT Lincoln Laboratory (MIT-LL). To accelerate development efforts and meet the AXIS mission requirements, XOC has developed a twin beamline testing system, capable of providing the necessary performance, flexibility, and robustness. We present design details, simulations, and performance results for the newer of the two beamlines, constructed and optimized to test and characterize the first full-size MIT-LL AXIS prototype detectors, operating with the Stanford-developed Multi-Channel Readout Chip (MCRC) integrated readout electronics system. The XOC X-ray beamline design is forward-looking and flexible, with a modular structure adaptable to a wide range of detector technologies identified by the Great Observatories Maturation Program (GOMAP) that span the X-ray to near-infrared wavelengths.

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Demonstrating sub-electron noise performance in Single electron Sensitive Readout (SiSeRO) devices

Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detection technology that can, in principle, provide significantly greater responsivity and improved noise performance than traditional charge coupled device (CCD) readout circuitry. The SiSeRO, developed by MIT Lincoln Laboratory, uses a p-MOSFET transistor with a depleted back-gate region under the transistor channel; as charge is transferred into the back gate region, the transistor current is modulated. With our first generation SiSeRO devices, we previously achieved a responsivity of around 800 pA per electron, an equivalent noise charge (ENC) of 4.5 electrons root mean square (RMS), and a full width at half maximum (FWHM) spectral resolution of 130 eV at 5.9 keV, at a readout speed of 625 Kpixel/s and for a detector temperature of 250 K. Importantly, since the charge signal remains unaffected by the SiSeRO readout process, we have also been able to implement Repetitive Non-Destructive Readout (RNDR), achieving an improved ENC performance. In this paper, we demonstrate sub-electron noise sensitivity with these devices, utilizing an enhanced test setup optimized for RNDR measurements, with excellent temperature control, improved readout circuitry, and advanced digital filtering techniques. We are currently fabricating new SiSeRO detectors with more sensitive and RNDR-optimized amplifier designs, which will help mature the SiSeRO technology in the future and eventually lead to the pathway to develop active pixel sensor (APS) arrays using sensitive SiSeRO amplifiers on each pixel. Active pixel devices with sub-electron sensitivity and fast readout present an exciting option for next generation, large area astronomical X-ray telescopes requiring fast, low-noise megapixel imagers.

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The XOC X-ray Beamline: Probing Colder, Quieter, and Softer

Future strategic X-ray satellite telescopes, such as the probe-class Advanced X-ray Imaging Satellite (AXIS), will require excellent soft energy response in their imaging detectors to enable maximum discovery potential. In order to characterize Charge-Coupled Device (CCD) and Single Electron Sensitive Read Output (SiSeRO) detectors in the soft X-ray region, the X-ray Astronomy and Observational Cosmology (XOC) group at Stanford has developed, assembled, and commissioned a 2.5-meter-long X-ray beamline test system. The beamline is designed to efficiently produce monoenergetic X-ray fluorescence lines in the 0.3-10 keV energy range and achieve detector temperatures as low as 173 K. We present design and simulation details of the beamline, and discuss the vacuum, cooling, and X-ray fluorescence performance achieved. As a workhorse for future detector characterization at Stanford, the XOC beamline will support detector development for a broad range of X-ray astronomy instruments.

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X-ray speed reading with the MCRC: prototype success and next generation upgrades

The Advanced X-ray Imaging Satellite (AXIS) is a NASA probe class mission concept designed to deliver arcsecond resolution with an effective area ten times that of Chandra (at launch). The AXIS focal plane features an MIT Lincoln Laboratory (MIT-LL) X-ray charge-coupled device (CCD) detector working in conjunction with an application specific integrated circuit (ASIC), denoted the Multi-Channel Readout Chip (MCRC). While this readout ASIC targets the AXIS mission, it is applicable to a range of potential X-ray missions with comparable readout requirements. Designed by the X-ray astronomy and Observational Cosmology (XOC) group at Stanford University, the MCRC ASIC prototype (MCRC-V1.0) uses a 350 nm technology node and provides 8 channels of high speed, low noise, low power consumption readout electronics. Each channel implements a current source to bias the detector output driver, a preamplifier to provide gain, and an output buffer to interface directly to an analog-to-digital (ADC) converter. The MCRC-V1 ASIC exhibits comparable performance to our best discrete electronics implementations, but with ten times less power consumption and a fraction of the footprint area. In a total ionizing dose (TID) test, the chip demonstrated a radiation hardness equal or greater to 25 krad, confirming the suitability of the process technology and layout techniques used in its design. The next iteration of the ASIC (MCRC-V2) will expand the channel count and extend the interfaces to external circuits, advancing its readiness as a readout-on-a-chip solution for next generation X-ray CCD-like detectors. This paper summarizes our most recent characterization efforts, including the TID radiation campaign and results from the first operation of the MCRC ASIC in combination with a representative MIT-LL CCD.

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Continued developments in X-ray speed reading: fast, low noise readout for next-generation wide-field imagers

Future strategic X-ray astronomy missions will require unprecedentedly sensitive wide-field imagers providing high frame rates, low readout noise and excellent soft energy response. To meet these needs, our team is employing a multi-pronged approach to advance several key areas of technology. Our first focus is on advanced readout electronics, specifically integrated electronics, where we are collaborating on the VERITAS readout chip for the Athena Wide Field Imager, and have developed the Multi-Channel Readout Chip (MCRC), which enables fast readout and high frame rates for MIT-LL JFET (junction field effect transistor) CCDs. Second, we are contributing to novel detector development, specifically the SiSeRO (Single electron Sensitive Read Out) devices fabricated at MIT Lincoln Laboratory, and their advanced readout, to achieve sub-electron noise performance. Hardware components set the stage for performance, but their efficient utilization relies on software and algorithms for signal and event processing. Our group is developing digital waveform filtering and AI methods to augment detector performance, including enhanced particle background screening and improved event characterization. All of these efforts make use of an efficient, new X-ray beamline facility at Stanford, where components and concepts can be tested and characterized.

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Towards efficient machine-learning-based reduction of the cosmic-ray induced background in X-ray imaging detectors: increasing context awareness

Traditional cosmic ray filtering algorithms used in X-ray imaging detectors aboard space telescopes perform event reconstruction based on the properties of activated pixels above a certain energy threshold, within 3x3 or 5x5 pixel sliding windows. This approach can reject up to 98% of the cosmic ray background. However, the remaining unrejected background constitutes a significant impediment to studies of low surface brightness objects, which are especially prevalent in the high-redshift universe. The main limitation of the traditional filtering algorithms is their ignorance of the long-range contextual information present in image frames. This becomes particularly problematic when analyzing signals created by secondary particles produced during interactions of cosmic rays with body of the detector. Such signals may look identical to the energy deposition left by X-ray photons, when one considers only the properties within the small sliding window. Additional information is present, however, in the spatial and energy correlations between signals in different parts of the frame, which can be accessed by modern machine learning (ML) techniques. In this work, we continue the development of an ML-based pipeline for cosmic ray background mitigation. Our latest method consist of two stages: first, a frame classification neural network is used to create class activation maps (CAM), localizing all events within the frame; second, after event reconstruction, a random forest classifier, using features obtained from CAMs, is used to separate X-ray and cosmic ray features. The method delivers >40% relative improvement over traditional filtering in background rejection in standard 0.3-10keV energy range, at the expense of only a small (<2%) level of lost X-ray signal. Our method also provides a convenient way to tune the cosmic ray rejection threshold to adapt to a user's specific scientific needs.

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