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Petros Karamanakos

Publications and source records attributed to Petros Karamanakos.

6 recordsLinked to original sources

Optimization of Current Lookup Tables for Minimum Stator Copper Loss and Torque Ripple in the Full Torque-Speed Range for a Six-Phase PMSM With Nonsinusoidal Back-EMF

A recently proposed method was able to generate current references with minimum stator copper loss (SCL) and torque ripple over the full torque-speed range of multiphase nonsalient permanent-magnet synchronous machines (PMSMs) with nonsinusoidal back-electromotive force (back-EMF). However, it relied on large lookup tables (LUTs) generated offline, requiring several hours for generation and large memory for storage. Since on-chip memory in industrial digital signal processors (DSPs) is limited, this hinders practical implementation. This paper addresses this problem by analyzing how the LUTs of that method can be simplified and optimized, focusing on the example of a symmetrical six-phase PMSM drive. Breakpoint selection (BS), LUT construction (LC), and interpolation approaches are evaluated to optimize the tradeoff between LUT simplification and performance. It is shown that the required memory and LUT generation time can be greatly reduced while keeping nearly the same feasible torque-speed area and performance. Simulation results confirm negligible performance degradation.

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Current References for Minimum Copper Loss and Torque Ripple in the Full Torque-Speed Range for Symmetrical Six-Phase PMSMs With Nonsinusoidal Back-EMF Under an Open-Phase Fault

Current-reference generation based on lookup tables (LUTs) is here proposed for star-connected symmetrical six-phase nonsalient PMSMs with nonsinusoidal back-EMF under an open-phase fault. Fourier coefficients for all healthy phases are computed offline, enabling unbalanced nonsinusoidal currents. A lexicographic optimization minimizes torque ripple and then copper loss, subject to torque, zero-current-sum, peak-current, peak-voltage, and torque-ripple constraints. Cogging torque can be included for compensation. Simulations show a higher feasible speed limit: about 30% at low torque and 23% along an example load curve. Finite-element analysis shows a 77% reduction in peak-to-peak torque ripple with cogging-torque compensation.

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Bounding the Minimal Current Harmonic Distortion in Optimal Modulation of Single-Phase Power Converters

Optimal pulse patterns (OPPs) are a modulation technique in which a switching signal is computed offline through an optimization process that accounts for selected performance criteria, such as current harmonic distortion. The optimization determines both the switching angles (i.e., switching times) and the pattern structure (i.e., the sequence of voltage levels). This optimization task is a challenging mixed-integer nonconvex problem, involving integer-valued voltage levels and trigono metric nonlinearities in both the objective and the constraints. We address this challenge by reinterpreting OPP design as a periodic mode-selecting optimal control problem of a hybrid system, where selecting angles and levels corresponds to choosing jump times in a transition graph. This time-domain formulation enables the direct use of convex-relaxation techniques from optimal control, producing a hierarchy of semidefinite programs that lower-bound the minimal achievable harmonic distortion and scale subquadratically with the number of converter levels and switching angles. Numerical results demonstrate the effectiveness of the proposed approachs

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Optimal Pulse Patterns through a Hybrid Optimal Control Perspective

Optimal pulse patterns (OPPs) are a modulation method in which the switching angles and levels of a switching signal are computed via an offline optimization procedure to minimize a performance metric, typically the harmonic distortions of the load current. Additional constraints can be incorporated into the optimization problem to achieve secondary objectives, such as the limitation of specific harmonics or the reduction of power converter losses. The resulting optimization problem, however, is highly nonconvex, featuring a trigonometric objective function and constraints as well as both real- and integer-valued optimization variables. This work casts the task of OPP synthesis for a multilevel converter as an optimal control problem of a hybrid system. This problem is in turn lifted into a convex but infinite-dimensional conic program of occupation measures using established methods in convex relaxations of optimal control. Lower bounds on the minimum achievable harmonic distortion are acquired by solving a sequence of semidefinite programs via the moment-sum-of-squares hierarchy, where each semidefinite program scales in a jointly linear manner with the numbers of permitted switching transitions and converter voltage levels.

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Quantum Computing in the Computational Landscape of Power Electronics: Vision and Reality

Quantum computing is rapidly emerging as a promising technology for solving complex optimization problems that arise in various engineering fields. Therefore, it holds significant promise to transform the computational foundations of power electronics. Motivated by this potential, this paper adopts a visionary perspective to examine how quantum computing could influence the evolution of power electronics in areas such as converter design, control, modulation, simulation workflows, and beyond. Within this framework, the current status, limitations, and anticipated progress of quantum algorithms and hardware are discussed, together with their potential to enable efficient solutions to large-scale, multiobjective, mixed-integer optimization problems. To place these developments in context, the paper begins with a concise tutorial on fundamental concepts in quantum computing, serving as both an introduction to the field and a bridge to its potential applications in power electronics. As a first step in this direction, the use of quantum computing for solving offline mixed-integer optimization problems commonly encountered in power electronics is examined. To this end, a simplified power electronics design problem is reformulated as a quadratic unconstrained binary optimization (QUBO) problem and executed on quantum hardware, despite current limitations such as low qubit counts and hardware noise. This demonstration marks a pioneering step towards leveraging quantum computing in power electronics and motivates the value of early adoption and exploration. Building on these insights, the paper outlines a forward-looking vision in which quantum computing becomes an integral part of the computational landscape of power electronics, guiding its transition from classical to quantum-enabled design and operation.

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Constraints-Informed Neural-Laguerre Approximation of Nonlinear MPC with Application in Power Electronics

This paper considers learning online (implicit) nonlinear model predictive control (MPC) laws using neural networks and Laguerre functions. Firstly, we parameterize the control sequence of nonlinear MPC using Laguerre functions, which typically yields a smoother control law compared to the original nonlinear MPC law. Secondly, we employ neural networks to learn the coefficients of the Laguerre nonlinear MPC solution, which comes with several benefits, namely the dimension of the learning space is dictated by the number of Laguerre functions and the complete predicted input sequence can be used to learn the coefficients. To mitigate constraints violation for neural approximations of nonlinear MPC, we develop a constraints-informed loss function that penalizes the violation of polytopic state constraints during learning. Box input constraints are handled by using a clamp function in the output layer of the neural network. We demonstrate the effectiveness of the developed framework on a nonlinear buck-boost converter model with sampling rates in the sub-millisecond range, where online nonlinear MPC would not be able to run in real time. The developed constraints-informed neural-Laguerre approximation yields similar performance with long-horizon online nonlinear MPC, but with execution times of a few microseconds, as validated on a field-programmable gate array (FPGA) platform.

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