arXiv subjects

Q. Sun

Publications and source records attributed to Q. Sun.

At least 19 recordsLinked to original sources

arXiv2024

Laser-synthesized TiN nanoparticles as novel efficient sorbent for environmental water cleaning

Dyes used in industries such as textile, paper, and leather are known to be harmful to both human health and aquatic ecosystems. Therefore, finding effective and sustainable methods to remove dyes from wastewater is crucial for mitigating the detrimental effects of pollution.TiN nanoparticles have good absorption and conversion of light energy into thermal energy in the visible range of the spectrum, which makes them promising in various applications, from biomedical to environmental protection. In this work, it is shown that titanium nitride nanoparticles also possess promising adsorption capabilitieseffect. TiN nanoparticles were synthesized by laser ablation method in liquid. Water, acetone and acetonitrile are used as solvent. Nanoparticles were characterized by scanning and transmission microscopy, Raman spectroscopy, which showed the formation of the under-stoichiometric titanium nitride (TiN1-x). TiN nanoparticles are investigated as a promising object for high adsorption It is shown that adsorption of TiN nanoparticles is associated with the electrostatic effect and the presence of pores in the synthesized nanoparticles. Optimal dye absorption capabilities were found to be associated with a low amount of Ti vacancies and high amount of N vacancies acting as donor states. The particles synthesized in water have the highest sorption capacity of dye achieving the value of 136.5 mg/g.

cond-mat.mtrl-sci↗

arXiv2023

GBT20, a 20.48 Gbps PAM4 Optical Transmitter Module for Particle Physics Experiments

We present a pluggable radiation-tolerant 4-level Pulse-Amplitude-Modulation (PAM4) optical transmitter module called GBT20 (Giga-Bit Transmitter at 20 Gbps) for particle-physics experiments. GBT20 has an OSFP or firefly connector to input 16-bit data each at 1.28 Gbps. The GBT20 drives a VCSEL die with an LC lens or a VCSEL TOSA and interfaces an optical fiber with a standard LC connector. The minimum module, including the host connector, occupies 41 mm x 13 mm x 6 mm. At 20.48 Gbps, the minimum Transmitter Dispersion Eye Closure Quaternary (TDECQ) is around 0.7 dB. The power consumption is around 164 mW in the low-power mode. The SEE cross-section is below 7.5x10^(-14) cm^2. No significant performance degrades after a TID of 5.4 kGy.

physics.ins-det↗

arXiv2023

An FPGA-based readout chip emulator for the CMS ETL detector upgrade

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

physics.ins-det↗

arXiv2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

physics.ins-det↗

arXiv2022

Electronics for Fast Timing

Picosecond-level timing will be an important component of the next generation of particle physics detectors. The ability to add a 4$^{th}$ dimension to our measurements will help address the increasing complexity of events at hadron colliders and provide new tools for precise tracking and calorimetry for all experiments. Detectors are described in detail on other whitepapers. In this note, we address challenges in electronics design for the new generations of fast timing detectors

physics.ins-det↗

arXiv2022

A 40 Gbps Optical Transceiver for Particle Physics Experiments

We present the design and the test results of a quad-channel optical transceiver module (QTRx) possibly for future particle physics experiments. The transmitters of QTRx, each at 10 Gbps, are based on a Quad-channel VCSEL Diode array Driver (QLDD) and 1 x 4 VCSEL array. The receivers of QTRx, with data rates of 2.56 Gbps or 10 Gbps per channel, are based on a Quad-channel Trans-Impedance and limiting Amplifier (QTIA) and 1 x 4 photodiode array of GaAs or InGaAs. QTRx is 20 mm x 10 mm x 5 mm and couples to an MT fiber connector. Test results indicate that QTRx achieves the design goals with a power consumption of 124 mW per transmitter channel at 10 Gbps and 120 mW at 2.56 Gbps for the receiver channel with an on-chip charge pump. The sensitivities of QTIA are -17 dBm at 2.56 Gbps and -8 dBm at 10 Gbps, respectively. Further improvements with a gold-finger interface and a more compact optical lens are being designed.

physics.ins-det↗

arXiv2022

Direct laser cooling of calcium monohydride molecules

We demonstrate optical cycling and sub-Doppler laser cooling of a cryogenic buffer-gas beam of calcium monohydride (CaH) molecules. We measure vibrational branching ratios for laser cooling transitions for both excited electronic states A and B. We measure further that repeated photon scattering via the $A\leftarrow X$ transition is achievable at a rate of $\sim$ $1.6\times10^6$ photons/s and demonstrate the interaction-time limited scattering of $\sim$ $200$ photons by repumping the largest vibrational decay channel. We also demonstrate the ability to sub-Doppler cool a molecular beam of CaH through the magnetically assisted Sisyphus effect. Using a standing wave of light, we lower the molecular beam's transverse temperature from $12.2(1.2)$ mK to $5.7(1.1)$ mK. We compare these results to sub-Doppler forces modeled using optical Bloch equations and Monte Carlo simulations of the molecular beam trajectories. This work establishes a clear pathway for creating a magneto-optical trap (MOT) of CaH molecules. Such a MOT could serve as a starting point for production of ultracold hydrogen gas via dissociation of a trapped CaH cloud.

physics.atom-ph↗

arXiv2022

A 20 Gbps PAM4 Data Transmitter ASIC for Particle Physics Experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

physics.ins-det↗

arXiv2021

A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.

physics.ins-det↗

arXiv2021

QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

physics.ins-det↗

arXiv2021

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16x16 pixel matrix.

physics.ins-det↗

arXiv2021

The orbital effect on the anomalous magnetism and evolution in La$_x$Y$_{1-x}$VO$_3$($0\le x \le 0.2$) single crystals

The orbital effect on the anomalous magnetism and evolution of low La-doping single crystals, La$_x$Y$_{1-x}$VO$_{3}$ (x = 0, 0.1, and 0.2), has been investigated by applying the X-ray diffraction, specific heat, magnetization and Raman scattering techniques. The larger nearest-neighbor (NN) exchange interaction along c-axis stabilizes the fluctuant G-type orbital ordering (G-OO) which favors the exotic C-type antiferromagnetic order (C-AF). It is found that the NN exchange interaction in ab plane is anisotropy relating to the in plane magnetic anisotropy, which becomes smaller in high La-doped sample. Most interestingly, with increasing the La$^{3+}$ content the orbital fluctuation and hybridization are decreased which stabilizes the C-OO phase and destabilizes the G-OO phase. Meanwhile, the diamagnetism in the exotic C-AF phase becomes weak and the possible mechanism relates to the change of the competition between the single-ion magnetic anisotropy and the Dzyaloshinsky-Moriya (DM) interaction with increasing x. Finally, the strong spin-orbital coupling has been observed at temperature just above T$_N$ in La$_{0.2}$Y$_{0.8}$VO$_{3}$ and a short range spin-orbital correlation is suggested.

cond-mat.str-el↗

arXiv2021

Hourly Warning for Strong Earthquakes

A promising perspective is presented that humans can provide hourly warning for strong land earthquakes (EQs, Ms6). Two important atmospheric electrostatic signal features are described. A table that lists 9 strong land EQs with shock time, epicenter, magnitude, weather in the region near the epicenter, precursor beginning time, and precursor duration demonstrates that at approximately several hours to one day before a strong land EQ, the weather conditions are fair near the epicenter, and an abnormal negative atmospheric electrostatic signal is very obvious. Moreover, the mechanism is explained. A method by which someone could determine the epicenter and the magnitude of a forthcoming strong EQ is suggested. Finally, the possibility of realizing hourly warning for strong land EQs in the near future is pointed out.

physics.geo-ph↗

arXiv2021

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16x16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. The measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

physics.ins-det↗

arXiv2020

A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps

We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.

physics.ins-det↗

arXiv2020

A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.

physics.ins-det↗

arXiv2020

A 4-Channel 10-Gbps/ch CMOS VCSEL Array Driver with on-chip Charge-pumps

We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser array driver, the cpVLAD. With on-chip charge-pumps to extend the biasing headroom for the VCSELs needed for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of driving VCSELs with forward bias voltages as high as 2.8 V from a 2.5 V power supply. The power consumption of the cpVLAD is 94 mW/ch.

physics.ins-det↗

arXiv2020

A TOSA/ROSA-Based Optical Transmitter (MTx+)/Transceiver (MTRx+) for High-Energy Physics Experiments

We present a dual-channel optical transmitter (MTx+)/transceiver (MTRx+) for the front-end readout electronics of high-energy physics experiments. MTx+ utilizes two Transmitter Optical Sub-Assemblies (TOSAs) and MTRx+ utilizes a TOSA and a Receiver Optical Sub-Assemblies (ROSA). Both MTx+ and MTRx+ receive multimode fibers with standard Lucent Connectors (LCs) as the optical interface and can be panel or board mounted to a motherboard with a standard Enhanced Small Form-factor Pluggable (SFP+) connector as the electrical interface. MTx+ and MTRx+ employ a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC called LOCld65, which brings the transmitting data rate up to 14 Gbps per channel. MTx+ and MTRx+ have been tested to survive 4.9 kGy(SiO2).

physics.ins-det↗