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Qi An

Publications and source records attributed to Qi An.

107 records · Page 6Linked to original sources

An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 μm CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a small channel-to-channel crosstalk and low ambient temperature dependency.

physics.ins-det↗

A Novel Method of Encoded Multiplexing Readout for Micro-pattern Gas Detectors

The requirement of a large number of electronic channels poses a big challenge for Micro-pattern Gas Detector (MPGD) to achieve good spatial resolution. By using the redundancy that at least two neighboring strips record the signal of a particle, a novel method of encoded multiplexing readout for MPGDs is presented in this paper. The method offers a feasible and easily-extensible way of encoding and decoding, and can significantly reduce the number of readout channels. A verification test was carried out on a 5*5 cm2 Thick Gas Electron Multiplier (THGEM) detector using a 8 keV Cu X-ray source with 100um slit, where 166 strips are read out by 21 encoded readout channels. The test results show a good linearity in its position response, and the spatial resolution root-mean-square (RMS) of the test system is about 260 μm. This method has an attractive potential to build large area detectors and can be easily adapted to other detectors like MPGDs.

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Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

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Application of Real-time Digitization Technique in Beam Measurement for Accelerators

Beam measurement is very important for accelerators. With the development of analog-to-digital conversion techniques, digital beam measurement becomes a research hot spot. IQ (In-phase & Quadrature-phase) analysis based method is an important beam measurement approach, the principle of which is presented and discussed in this paper. The State Key Laboratory of Particle Detection and Electronics in University of Science and Technology of China has devoted efforts to the research of digital beam measurement based on high-speed high-resolution analog-to-digital conversion, and a series of beam measurement instruments were designed for China Spallation Neutron Source (CSNS), Shanghai Synchrotron Radiation Facility (SSRF), and Accelerator Driven Sub-critical system (ADS).

physics.acc-ph↗

Single Event Effect Hardness for the Front-end ASICs Applied in BGO Calorimeter of DAMPE Satellite

Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effect (SEE) a probable threat to reliability. In order to evaluate the SEE sensitivity of the chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and optimized sequential design for data acquisition process, VA160 and VATA160 with the quantity of 54 and 32 respectively have been applied in the flight model of BGO calorimeter with radiation hardness assurance.

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The Analog Front-end Prototype Electronics Designed for LHAASO WCDA

In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the whole readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1% @ 4000 P.E. and remains better than 10% @ 1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than application requirement.

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Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 μm CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

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TOT Measurement Implemented in FPGA TDC

Time measurement plays a crucial rule for the purpose of particle identification in high energy physical experiments. With the upgrading of physical goal and the developing of electronics, modern time measurement system meets the requirement of excellent resolution specification as well as high integrity. Due to Field Programmable Gate Array (FPGA), FPGA time-to-digital converter (TDC) becomes one of mature and prominent time measurement methods in recent years. For correcting time-walk effect caused by leading timing, time-over-threshold (TOT) measurement should be added in the FPGA TDC. TOT can be obtained by measuring the interval time of signal leading and trailing edge. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels can be used at the same time, one for leading, the other for trailing. However, this method will increase the amount of used FPGA resource and reduce the TDC's integrity unavoidably. This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measure can be achieved in only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Test shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measuring dead time is about 2 clock cycles, which makes it be good for applications of higher physical event rate

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Waveform Timing Performance of a 5 GS/s Fast Pulse Sampling Module with DRS4

We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. Calibration strategy is proposed, and as a result, the waveform timing performance is improved to be below 10 ps RMS. We then further evaluate waveform timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.

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Design of the Readout Electronics for the Qualification Model of DAMPE BGO Calorimeter

The DAMPE (DArk Matter Particle Explorer) is a scientific satellite being developed in China, aimed at cosmic ray study, gamma ray astronomy, and searching for the clue of dark matter particles, with a planned mission period of more than 3 years and an orbit altitude of about 500 km. The BGO Calorimeter, which consists of 308 BGO (Bismuth Germanate Oxid) crystal bars, 616 PMTs (photomultiplier tubes) and 1848 dynode signals, has approximately 32 radiation lengths. It is a crucial sub-detector of the DAMPE payload, with the functions of precisely measuring the energy of cosmic particles from 5 GeV to 10TeV, distinguishing positrons/electrons and gamma rays from hadron background, and providing trigger information for the whole DAMPE payload. The dynamic range for a single BGO crystal is about 2?105 and there are 1848 detector signals in total. To build such an instrument in space, the major design challenges for the readout electronics come from the large dynamic range, the high integrity inside the very compact structure, the strict power supply budget and the long term reliability to survive the hush environment during launch and in orbit. Currently the DAMPE mission is in the end of QM (Qualification Model) stage. This paper presents a detailed description of the readout electronics for the BGO calorimeter.

astro-ph.IM↗

Study on FPGA SEU Mitigation for Readout Electronics of DAMPE BGO Calorimeter

The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based FPGA, of which the design-level flip-flops and embedded block RAMs are single event upset (SEU) sensitive in the harsh space environment. Therefore to comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

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A Compact PCI-based Measurement and Control System for Satellite-Ground Quantum Communication

Since the 1990s, there has been a dramatic interest in quantum communication. Free-space quantum communication is being developed to ultra-long distance quantum experiment, which requires higher electronics performance, such as time measurement precision, data-transfer rate, and system integration density. As part of the ground station of quantum experiment satellite that will be launched in 2016, we specifically designed a compact PCI-based multi-channel electronics system with high time-resolution, high data-transfer-rate. The electronics performance of this system was tested. The time bin size is 23.9ps and the time precision root-mean-square (RMS) is less than 24ps for 16 channels. The dead time is 30ns. The data transfer rate to local computer is up to 35 MBps, and the count rate is up to 30M/s. The system has been proven to perform well and operate stably through a test of free space quantum key distribution (QKD) experiment.

quant-ph↗

A Multi-chain Measurements Averaging TDC Implemented in a 40 nm FPGA

A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain number is M), and there is a fixed delay cell between every two adjacent chains. Each tapped-delay chain is just a plain TDC and should generate a TDC time for a hit input signal, so totally M TDC time values should be got for a hit signal. After averaging, the final TDC time is obtained. A TDC with 3 ps resolution (i.e. bin size) and 6.5 ps precision (i.e. RMS) has been implemented using 8 parallel tapped-delay chains. Meanwhile the plain TDC with single tapped-delay chain yields 24 ps resolution and 18 ps precision.

physics.ins-det↗

Development of COTS ADC SEE Test System for the ATLAS LAr Calorimeter Upgrade

Radiation-tolerant, high speed, high density and low power commercial off-the-shelf (COTS) analog-to-digital converters (ADCs) are planned to be used in the upgrade to the Liquid Argon (LAr) calorimeter front end (FE) trigger readout electronics. Total ionization dose (TID) and single event effect (SEE) are two important radiation effects which need to be characterized on COTS ADCs. In our initial TID test, Texas Instruments (TI) ADS5272 was identified to be the top performer after screening a total 17 COTS ADCs from different manufacturers with dynamic range and sampling rate meeting the requirements of the FE electronics. Another interesting feature of ADS5272 is its 6.5 clock cycles latency, which is the shortest among the 17 candidates. Based on the TID performance, we have designed a SEE evaluation system for ADS5272, which allows us to further assess its radiation tolerance. In this paper, we present a detailed design of ADS5272 SEE evaluation system and show the effectiveness of this system while evaluating ADS5272 SEE characteristics in multiple irradiation tests. According to TID and SEE test results, ADS5272 was chosen to be implemented in the full-size LAr Trigger Digitizer Board (LTDB) demonstrator, which will be installed on ATLAS calorimeter during the 2014 Long Shutdown 1 (LS1).

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A new method of waveform digitization based on time-interleaved A/D conversion

Time interleaved analog-to-digital conversion (TIADC) based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limitation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit 1-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.

physics.ins-det↗

Proposal of the Readout Electronics for the WCDA in LHAASO Experiment

The LHAASO (Large High Altitude Air Shower Observatory) experiment is proposed for very high energy gamma ray source survey, in which the WCDA (Water Cherenkov Detector Array) is the one of the major components. In the WCDA, a total of 3600 PMTs are placed under water in four ponds, each with a size of 150 m x 150 m. Precise time and charge measurement is required for the PMT signals, over a large signal amplitude range from single P.E. (photo electron) to 4000 P.E. To fulfill the high requirement of signal measurement in so many front end nodes scattered in a large area, special techniques are developed, such as multiple gain readout, hybrid transmission of clocks, commands, and data, precise clock phase alignment, and new trigger electronics. We present the readout electronics architecture for the WCDA and several prototype modules, which are now under test in the laboratory.

astro-ph.IM↗

A Fast Improved Fat Tree Encoder for Wave Union TDC in an FPGA

Up to the present, the wave union method can achieve the best timing performance in FPGA based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands the encoder to convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constrains were required; therefore, this IFTE structure could also be further applied in other delay chain based FPGA TDCs.

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