arXiv subjects

R. D. Mawhinney

Publications and source records attributed to R. D. Mawhinney.

41 records · Page 3Linked to original sources

arXiv2006

The Kaon B-parameter from Quenched Domain-Wall QCD

We present numerical results for the kaon B-parameter, B_K, determined in the quenched approximation of lattice QCD. Our simulations are performed using domain-wall fermions and the renormalization group improved, DBW2 gauge action which combine to give quarks with good chiral symmetry at finite lattice spacing. Operators are renormalized non-perturbatively using the RI/MOM scheme. We study scaling by performing the simulation on two different lattices with a^{-1} = 1.982(30) and 2.914(54) GeV. We combine this quenched scaling study with an earlier calculation of B_K using two flavors of dynamical, domain-wall quarks at a single lattice spacing to obtain B_K(MS,NDR,mu=2GeV)=0.563(21)(39)(30), were the first error is statistical, the second systematic (without quenching errors) and the third estimates the error due to quenching.

hep-lat↗

arXiv2003

Hardware and software status of QCDOC

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

hep-lat↗

arXiv2002

Status of and performance estimates for QCDOC

QCDOC is a supercomputer designed for high scalability at a low cost per node. We discuss the status of the project and provide performance estimates for large machines obtained from cycle accurate simulation of the QCDOC ASIC.

hep-lat↗

arXiv2001

Status of the QCDOC project

A status report is given of the QCDOC project, a massively parallel computer optimized for lattice QCD using system-on-a-chip technology. We describe several of the hardware and software features unique to the QCDOC architecture and present performance figures obtained from simulating the current VHDL design of the QCDOC chip with single-cycle accuracy.

hep-lat↗

arXiv2000

QCDOC: A 10-teraflops scale computer for lattice QCD

The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from ``QCD On a Chip''.

hep-lat↗