arXiv subjects

Ritajit Majumdar

Publications and source records attributed to Ritajit Majumdar.

At least 19 recordsLinked to original sources

arXiv2026

Lightweight Targeted Estimation of Layout Noise in a Quantum Computer using Quality Indicator Circuits

Minimizing noise is essential for reliably executing quantum circuits on the current generation of hardware. The mapping of an abstract quantum circuit to the physical layout of the quantum hardware significantly influences the output quality since hardware noise profiles are non-uniform and dynamic. Existing solutions such as Mapomatic relies on stale calibrations while Just-In-Time (JIT) Transpilation has high hardware usage. We propose Quality Indicator Circuits (QICs) as a lightweight probe circuit synthesized from the user circuit, whose ideal noiseless outcome is known. QIC helps decide the region of the quantum hardware best suited for the given circuit. We propose QIC execution for each isomorphic layout, and an alternative approach where a union of multiple layouts are executed together for lower overheads. Our results show QIC to outperform Mapomatic in the quality of layout selection while having 79 percent lower hardware overheads than JIT. This makes our QIC method lightweight, reliable and a viable technique for layout selection in near-term quantum devices.

cs.ET↗

arXiv2026

Basis Adaptive Algorithm for Quantum Many-Body Systems on Quantum Computers

We introduce a Basis Adaptive (BA) algorithm for hybrid quantum-classical simulation of correlated quantum many-body systems. Starting from a small set of physically motivated bitstrings, the algorithm iteratively applies a single-step first-order Trotterized circuit on a quantum processor, filters the sampled configurations by enforcing $U(1)$ spin conservation and lattice reflection symmetry, and classically diagonalizes the Hamiltonian in the resulting reduced Hilbert space. This design avoids the variational optimization overhead of VQE, the deep coherent circuits required by QPE, and the symmetry-violating subspaces that arise in SKQD. The ground-state energy error is bounded analytically by $\sqrt{8}\,\|H\|\left(1-\sqrt{α_{D_T}}\right)^{1/2}$, where $α_{D_T}$ is the probability weight captured by the $D_T$ sampled basis states. This bound connects algorithm performance directly to ground-state sparsity and explains the observed accuracy hierarchy across different phases. Benchmarked on the spin-$1/2$ Heisenberg XXZ chain (up to $N=62$ qubits on the IBM Heron processor), the algorithm achieves a $3.5\%$ energy error in the gapped Neel phase ($Δ=2.0$) and below $0.5\%$ at the ferromagnetic boundary ($Δ=-1.0$). The accuracy degrades to $28.7\%$ in the strongly quasi-long-range-ordered regime ($Δ=0.5$). Spin-spin correlation functions are reproduced across all regimes, confirming that symmetry-filtered real-time sampling provides a practical and noise-resilient pathway to ground-state properties on near-term quantum hardware.

cond-mat.str-el↗

arXiv2026

Observation of Robust and Coherent Non-Abelian Hadron Dynamics on Noisy Quantum Processors

The real-time evolution of strongly interacting matter remains a frontier of fundamental physics, as classical simulations are hampered by exponential Hilbert space growth and rapid, unmanageable growth of quantum entanglement. This study reports the quantum simulation of hadron dynamics within a $(1+1)$-dimensional SU(2) lattice gauge theory using a 156-qubit IBM superconducting processor. Leveraging a hardware-efficient Loop-String-Hadron (LSH) encoding, we simulate the dynamics of the physical degrees of freedom on a $60$-site lattice in the weak-coupling regime, as a crucial step toward the continuum limit. The hardware data reveal confined meson propagation and early-time oscillations of the mesonic profile, from which we extract a breathing-mode frequency as a spectroscopic observable. Benchmarking against tensor-network simulations of the full LSH Hamiltonian and Pauli-propagation simulations of the noiseless circuit supports the validity of the physical approximation, the quantum algorithm and the observed dynamics within the accessible time window. These results show that physics-native encodings can enable scalable access to coherent non-Abelian real-time dynamics on noisy quantum hardware.

hep-lat↗

arXiv2026

Noise-aware selection of circuit cutting strategies under hardware noise non-uniformity

Noise in contemporary quantum hardware is highly non-uniform across qubits and couplers, giving rise to localized low-noise "islands" within otherwise noisy device topologies. As quantum workloads scale, executions are increasingly forced to traverse high-noise regions, degrading algorithmic fidelity. Circuit cutting provides a route to circumvent such regions by decomposing large circuits into smaller subcircuits, but its practicality is limited by exponential sampling overhead and the lack of systematic guidance on how cut strategies should align with heterogeneous hardware noise. In this work, we present a hardware-noise-aware circuit cutting framework that explicitly exploits the spatial non-uniformity of noise in quantum devices. Rather than proposing a new cut-finding algorithm, we formalize the problem of device-constraint selection under realistic hardware noise and show that this choice critically determines both execution overhead and effective noise. Using a unified gate- and wire-cutting formulation, we demonstrate that small, hardware-informed relaxations in the device constraint yield exponential reductions in execution overhead while preserving alignment with low-noise hardware regions. Across representative workloads, our method achieves an average reduction in the number of circuit executions ranging from 5-54x for 20-qubit circuits, and enables tractable circuit cutting for 50-qubit circuits and application-level benchmarks where conventional strategies incur prohibitive overhead. These results establish noise-aware device-constraint selection as a necessary ingredient for making circuit cutting resource-efficient and practically deployable on contemporary quantum hardware.

quant-ph↗

arXiv2025

Low overhead circuit cutting with operator backpropagation

Current quantum computers suffer from noise due to lack of error correction. Several techniques to mitigate the effect of noise have been studied, in particular to extract the expectation value of observables. One such technique, circuit cutting, partitions large circuits into smaller, less noisy subcircuits, but the exponential increase in the number of circuit executions limits its scalability. Another method, operator backpropagation (OBP) reduces circuit depth by classically simulating parts of it, yet often escalates the number of circuit executions by some factor due to additional non-commuting terms in the updated observable. This paper introduces an optimized approach for minimizing noise in quantum circuits using operator backpropagation (OBP) combined with circuit cutting. We demonstrate that the strategic use of OBP with circuit cutting can mitigate the execution overhead. By employing simulated annealing, our proposed method identifies the optimal backpropagation parameter for specific circuits and observables, maximizing resource reduction in cutting. Results show a 3x and 10x decrease in resource requirements for Variational Quantum Eigensolver and Hamiltonian simulation circuits respectively, while maintaining or even enhancing accuracy. This approach also yields similar savings for other circuits from the Benchpress database and various observable weights, providing an efficient method to lower circuit cutting overhead without compromising performance.

quant-ph↗

arXiv2025

Distributed Scheduling of Quantum Circuits with Noise and Time Optimization

Quantum computers are currently noisy, particularly without error correction and fault tolerance. Methods like error suppression and mitigation are widely used to improve performance. Circuit cutting, which partitions a circuit into smaller subcircuits, can also reduce noise. In this paper, we propose an Integer Linear Program (ILP) based scheduler for optimizing subcircuit schedules on available hardware. The goal is to maximize overall fidelity and ensure each hardware does not exceed its predefined execution time. For 10-qubit circuits, our method achieves an average fidelity improvement of ~12.3% and ~21% with and without measurement error mitigation, respectively, even with minimal execution time. Additionally, we introduce a polynomial-time graph-theoretic scheduling method that matches the ILP scheduler's results when the number of subcircuits does not exceed the number of hardware units, each with minimal execution time. This noise and time-optimized scheduler represents a crucial step towards optimal quantum computing performance, especially with limited hardware access.

quant-ph↗

arXiv2024

Diagonalization of large many-body Hamiltonians on a quantum processor

The estimation of low energies of many-body systems is a cornerstone of computational quantum sciences. Variational quantum algorithms can be used to prepare ground states on pre-fault-tolerant quantum processors, but their lack of convergence guarantees and impractical number of cost function estimations prevent systematic scaling of experiments to large systems. Alternatives to variational approaches are needed for large-scale experiments on pre-fault-tolerant devices. Here, we use a superconducting quantum processor to compute eigenenergies of quantum many-body systems on two-dimensional lattices of up to 56 sites, using the Krylov quantum diagonalization algorithm, an analog of the well-known classical diagonalization technique. We construct subspaces of the many-body Hilbert space using Trotterized unitary evolutions executed on the quantum processor, and classically diagonalize many-body interacting Hamiltonians within those subspaces. These experiments show that quantum diagonalization algorithms are poised to complement their classical counterpart at the foundation of computational methods for quantum systems.

quant-ph↗

arXiv2024

Resource-aware scheduling of multiple quantum circuits on a hardware device

Recent quantum technologies and quantum error-correcting codes emphasize the requirement for arranging interacting qubits in a nearest-neighbor (NN) configuration while mapping a quantum circuit onto a given hardware device, in order to avoid undesirable noise. It is equally important to minimize the wastage of qubits in a quantum hardware device with m qubits while running circuits of n qubits in total, with n < m. In order to prevent cross-talk between two circuits, a buffer distance between their layouts is needed. Furthermore, not all the qubits and all the two-qubit interactions are at the same noise-level. Scheduling multiple circuits on the same hardware may create a possibility that some circuits are executed on a noisier layout than the others. In this paper, we consider an optimization problem which schedules as many circuits as possible for execution in parallel on the hardware, while maintaining a pre-defined layout quality for each. An integer linear programming formulation to ensure maximum fidelity while preserving the nearest neighbor arrangement among interacting qubits is presented. Our assertion is supported by comprehensive investigations involving various well-known quantum circuit benchmarks. As this scheduling problem is shown to be NP Hard, we also propose a greedy heuristic method which provides 2x and 3x better utilization for 27-qubit and 127-qubit hardware devices respectively in terms of qubits and time.

quant-ph↗

arXiv2024

Efficient Syndrome Decoder for Heavy Hexagonal QECC via Machine Learning

Error syndromes for heavy hexagonal code and other topological codes such as surface code have typically been decoded by using Minimum Weight Perfect Matching (MWPM) based methods. Recent advances have shown that topological codes can be efficiently decoded by deploying machine learning (ML) techniques, in particular with neural networks. In this work, we first propose an ML based decoder for heavy hexagonal code and establish its efficiency in terms of the values of threshold and pseudo-threshold, for various noise models. We show that the proposed ML based decoding method achieves $\sim5 \times$ higher values of threshold than that for MWPM. Next, exploiting the property of subsystem codes, we define gauge equivalence for heavy hexagonal code, by which two distinct errors can belong to the same error class. A linear search based method is proposed for determining the equivalent error classes. This provides a quadratic reduction in the number of error classes to be considered for both bit flip and phase flip errors, and thus a further improvement of $\sim 14\%$ in the threshold over the basic ML decoder. Lastly, a novel technique based on rank to determine the equivalent error classes is presented, which is empirically faster than the one based on linear search.

cs.IT↗

arXiv2023

On Fault Tolerance of Circuits with Intermediate Qutrit-assisted Gate Decomposition

The use of a few intermediate qutrits for efficient decomposition of 3-qubit unitary gates has been proposed, to obtain an exponential reduction in the depth of the decomposed circuit. An intermediate qutrit implies that a qubit is operated as a qutrit in a particular execution cycle. This method, primarily for the NISQ era, treats a qubit as a qutrit only for the duration when it requires access to the state $\ket{2}$ during the computation. In this article, we study the challenges of including fault-tolerance in such a decomposition. We first show that any qubit that requires access to the state $\ket{2}$ at any point in the circuit, must be encoded using a qutrit quantum error correcting code (QECC), thus resulting in a circuit with both qubits and qutrits at the outset. Since qutrits are noisier than qubits, the former is expected to require higher levels of concatenation to achieve a particular accuracy than that for qubit-only decomposition. Next, we derive analytically (i) the number of levels of concatenation required for qubit-qutrit and qubit-only decompositions as a function of the probability of error, and (ii) the criterion for which qubit-qutrit decomposition leads to a lower gate count than qubit-only decomposition. We present numerical results for these two types of decomposition and obtain the situation where qubit-qutrit decomposition excels for the example circuit of the quantum adder by considering different values for quantum hardware-noise and non-transversal implementation of the 2-controlled ternary CNOT gate.

quant-ph↗

arXiv2023

Best practices for quantum error mitigation with digital zero-noise extrapolation

Digital zero-noise extrapolation (dZNE) has emerged as a common approach for quantum error mitigation (QEM) due to its conceptual simplicity, accessibility, and resource efficiency. In practice, however, properly applying dZNE to extend the computational reach of noisy quantum processors is rife with subtleties. Here, based on literature review and original experiments on noisy simulators and real quantum hardware, we define best practices for QEM with dZNE for each step of the workflow, including noise amplification, execution on the quantum device, extrapolation to the zero-noise limit, and composition with other QEM methods. We anticipate that this effort to establish best practices for dZNE will be extended to other QEM methods, leading to more reproducible and rigorous calculations on noisy quantum hardware.

quant-ph↗

arXiv2023

Parallelizing Quantum-Classical Workloads: Profiling the Impact of Splitting Techniques

Quantum computers are the next evolution of computing hardware. Quantum devices are being exposed through the same familiar cloud platforms used for classical computers, and enabling seamless execution of hybrid applications that combine quantum and classical components. Quantum devices vary in features, e.g., number of qubits, quantum volume, CLOPS, noise profile, queuing delays and resource cost. So, it may be useful to split hybrid workloads with either large quantum circuits or large number of quantum circuits, into smaller units. In this paper, we profile two workload splitting techniques on IBM's Quantum Cloud: (1) Circuit parallelization, to split one large circuit into multiple smaller ones, and (2) Data parallelization to split a large number of circuits run on one hardware to smaller batches of circuits run on different hardware. These can improve the utilization of heterogenous quantum hardware, but involve trade-offs. We evaluate these techniques on two key algorithmic classes: Variational Quantum Eigensolver (VQE) and Quantum Support Vector Machine (QSVM), and measure the impact on circuit execution times, pre- and post-processing overhead, and quality of the result relative to a baseline without parallelization. Results are obtained on real hardware and complemented by simulations. We see that (1) VQE with circuit cutting is ~39\% better in ground state estimation than the uncut version, and (2) QSVM that combines data parallelization with reduced feature set yields upto 3x improvement in quantum workload execution time and reduces quantum resource use by 3x, while providing comparable accuracy. Error mitigation can improve the accuracy by ~7\% and resource foot-print by ~4\% compared to the best case among the considered scenarios.

quant-ph↗

arXiv2022

Error mitigated quantum circuit cutting

We investigate an error mitigated tomographic approach to the quantum circuit cutting problem in the presence of gate and measurement noise. We explore two tomography specific error mitigation techniques; readout error mitigated conditional fragment tomography, which uses knowledge of readout errors on all cut and conditional qubit measurements in the tomography reconstruction procedure; and dominant eigenvalue truncation (DEVT), which aims to improve the performance of circuit cutting by performing truncation of the individual conditional tomography fragments used in the reconstruction. We find that the performance of both readout error mitigated tomography and DEVT tomography are comparable for circuit cutting in the presence of symmetric measurement errors. For gate errors our numerical results show that probability estimates for the original circuit obtained using DEVT outperforms general circuit cutting for measurement, depolarization and weakly biased Pauli noise models, but does not improve performance for amplitude damping and coherent errors, and can greatly decrease performance for highly biased Pauli noise. In cases where DEVT was effective, it as also found to improve performance of partial tomographic reconstruction using at least 50% of the full tomographic data with a conditional least-squares tomographic fitter, while linear inversion tomography with or without DEVT mitigation was found to perform poorly with with partial data.

quant-ph↗

arXiv2022

Thermal relaxation error on QKD: Effect and A Probable Bypass

Quantum cryptography was proposed as a counter to the capacity of quantum computers to break classical cryptosystems. A broad subclass of quantum cryptography, called quantum key distribution (QKD), relies on quantum mechanical process for secure distribution of the keys. Quantum channels are inherently noisy, and therefore these protocols will be susceptible to noise as well. In this paper, we study the performance of two QKD protocols - BB84 and E91 under thermal relaxation error. We show that while E91 protocol loses its security immediately due to loss of entanglement, the performance of BB84 protocol reduces to random guessing with increasing time. Next, we consider the action of an Eve on the BB84 protocol under thermal relaxation noise, who is restricted to guessing the outcome of the protocol only. Under this restriction, we show that Eve can still do better than random guessing when equipped with the characteristics of the noisy channel. Finally, we propose a modification of the BB84 protocol which retains the security of the original protocol, but ensures that Eve cannot get any advantage in guessing the outcome, even with a complete channel information.

quant-ph↗

arXiv2022

Surface Code Design for Asymmetric Error Channels

Surface codes are quantum error correcting codes normally defined on 2D arrays of qubits. In this paper, we introduce a surface code design based on the fact that the severity of bit flip and phase flip errors in the physical quantum systems is asymmetric. For our proposed surface code design for asymmetric error channels, we present pseudo-threshold and threshold values in the presence of various degrees of asymmetry of Pauli $\hat{X}$, $\hat{Y}$, and $\hat{Z}$ errors in a depolarization channel. We show that, compared to symmetric surface codes, our asymmetric surface codes can provide almost double the pseudo-threshold rates while requiring less than half the number of physical qubits in the presence of increasing asymmetry in the error channel. We also demonstrate that as the asymmetry of the surface code increases, the advantage in the pseudo-threshold rates begins to saturate for any degree of asymmetry in the channel.

quant-ph↗

arXiv2022

Asymptotically Improved Circuit for $d$-ary Grover's Algorithm with Advanced Decomposition of $n$-qudit Toffoli Gate

The progress in building quantum computers to execute quantum algorithms has recently been remarkable. Grover's search algorithm in a binary quantum system provides considerable speed-up over classical paradigm. Further, Grover's algorithm can be extended to a $d$-ary (qudit) quantum system for utilizing the advantage of larger state space, which helps to reduce the run-time of the algorithm as compared to the traditional binary quantum systems. In a qudit quantum system, an $n$-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this article, a generalized $n$-qudit Toffoli gate has been realized using higher dimensional qudits to attain a logarithmic depth decomposition without ancilla qudit. The circuit for Grover's algorithm has then been designed for any $d$-ary quantum system, where $d \ge 2$, with the proposed $n$-qudit Toffoli gate to obtain optimized depth compared to earlier approaches. The technique for decomposing an $n$-qudit Toffoli gate requires access to two immediately higher energy levels, making the design susceptible to errors. Nevertheless, we show that the percentage decrease in the probability of error is significant as we have reduced both gate count and circuit depth as compared to that in state-of-the-art works.

quant-ph↗

arXiv2021

Efficient Decoding of Surface Code Syndromes for Error Correction in Quantum Computing

Errors in surface code have typically been decoded by Minimum Weight Perfect Matching (MWPM) based method. Recently, neural-network-based Machine Learning (ML) techniques have been employed for this purpose. Here we propose a two-level (low and high) ML-based decoding scheme, where the first level corrects errors on physical qubits and the second one corrects any existing logical errors, for different noise models. Our results show that our proposed decoding method achieves $\sim10 \times$ and $\sim2 \times$ higher values of pseudo-threshold and threshold respectively, than for MWPM. We show that usage of more sophisticated ML models with higher training/testing time, do not provide significant improvement in the decoder performance. Finally, data generation for training the ML decoder requires significant overhead hence lower volume of training data is desirable. We have shown that our decoder maintains a good performance with the train-test-ratio as low as $40:60$.

quant-ph↗

arXiv2021

Depth Optimized Ansatz Circuit in QAOA for Max-Cut

While a Quantum Approximate Optimization Algorithm (QAOA) is intended to provide a quantum advantage in finding approximate solutions to combinatorial optimization problems, noise in the system is a hurdle in exploiting its full potential. Several error mitigation techniques have been studied to lessen the effect of noise on this algorithm. Recently, Majumdar et al. proposed a Depth First Search (DFS) based method to reduce $n-1$ CNOT gates in the ansatz design of QAOA for finding Max-Cut in a graph G = (V, E), |V| = n. However, this method tends to increase the depth of the circuit, making it more prone to relaxation error. The depth of the circuit is proportional to the height of the DFS tree, which can be $n-1$ in the worst case. In this paper, we propose an $O(Δ\cdot n^2)$ greedy heuristic algorithm, where $Δ$ is the maximum degree of the graph, that finds a spanning tree of lower height, thus reducing the overall depth of the circuit while still retaining the $n-1$ reduction in the number of CNOT gates needed in the ansatz. We numerically show that this algorithm achieves nearly 10 times increase in the probability of success for each iteration of QAOA for Max-Cut. We further show that although the average depth of the circuit produced by this heuristic algorithm still grows linearly with n, our algorithm reduces the slope of the linear increase from 1 to 0.11.

quant-ph↗