arXiv subjects

Ruo-Tong Chen

Publications and source records attributed to Ruo-Tong Chen.

4 recordsLinked to original sources

arXiv2026

BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement

Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades. Early BBO efforts, however, were limited by immature problem formulations and inefficient algorithm designs, leading to worse efficiency, quality, and scalability than mainstream analytical methods. Recent advances in BBO have shown strong potential, but a unified, BBO-specific benchmark for thoroughly assessing various problem formulations and BBO algorithms is lacking. To fill this gap, we propose BBOPlace-Bench, the first benchmark tailored for evaluating and developing BBO algorithms for chip placement. It integrates three BBO problem formulations and offers a modular, flexible framework that enables users to seamlessly implement, test, and compare their own algorithms. It aggregates representative modern chip cases and standardizes their formats, providing uniform and comprehensive information to support BBO optimization. Moreover, it integrates representative BBO algorithm families, including simulated annealing, population-based search (including GA, CMA-ES, and PSO), and Bayesian optimization, and systematically evaluates their performance across different problem formulations using key chip-placement metrics. We position these experiments primarily as illustrative case studies under a shared evaluation protocol, including common benchmark instances, metric definitions, evaluation pipeline, and search budgets. Under this protocol, some BBO configurations (e.g., GA under the mask-guided optimization formulation) are competitive with representative analytical and reinforcement learning baselines. BBOPlace-Bench not only facilitates the development of efficient BBO-driven solutions for chip placement but also broadens the practical application scenarios urgently needed by the BBO community.

cs.LG↗

arXiv2026

FlowPlace: Flow Matching for Chip Placement

Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50$\times$ faster sampling efficiency, and zero overlaps.

cs.AR↗

arXiv2026

How Can Reinforcement Learning Achieve Expert-level Placement?

Chip placement is a critical step in physical design. While reinforcement learning (RL)-based methods have recently emerged, their training primarily focuses on wirelength optimization, and therefore often fail to achieve expert-quality layouts. We identify the reward design as the primary cause for the performance gap with experts, and instead of formalizing intricate processes, we circumvent this by directly learning from expert layouts to derive a reward model. Our approach starts from the final expert layouts to infer step-by-step expert trajectories. Using these trajectories as demonstrations or preferences, we train a model that captures the latent implicit rewards in expert results. Experiments show that our framework can efficiently learn from even a single design and generalize well to unseen cases.

cs.AR↗

arXiv2024

Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer

In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics. Recently, reinforcement learning (RL) has emerged as a promising technique for improving placement quality, especially macro placement. However, current RL-based placement methods suffer from long training times, low generalization ability, and inability to guarantee PPA results. A key issue lies in the problem formulation, i.e., using RL to place from scratch, which results in limits useful information and inaccurate rewards during the training process. In this work, we propose an approach that utilizes RL for the refinement stage, which allows the RL policy to learn how to adjust existing placement layouts, thereby receiving sufficient information for the policy to act and obtain relatively dense and precise rewards. Additionally, we introduce the concept of regularity during training, which is considered an important metric in the chip design industry but is often overlooked in current RL placement methods. We evaluate our approach on the ISPD 2005 and ICCAD 2015 benchmark, comparing the global half-perimeter wirelength and regularity of our proposed method against several competitive approaches. Besides, we test the PPA performance using commercial software, showing that RL as a regulator can achieve significant PPA improvements. Our RL regulator can fine-tune placements from any method and enhance their quality. Our work opens up new possibilities for the application of RL in placement, providing a more effective and efficient approach to optimizing chip design. Our code is available at \url{https://github.com/lamda-bbo/macro-regulator}.

cs.LG↗