arXiv subjects

S. Kulis

Publications and source records attributed to S. Kulis.

16 recordsLinked to original sources

arXiv2024

Functional Verification for Endcap Concentrator ASICs in the High-Granularity Calorimeter Upgrade of CMS

The High-Granularity Calorimeter (HGCAL) will replace the current CMS Endcap Calorimeter during Long-Shutdown 3. The Endcap Concentrator (ECON) ASICs represent key elements in the readout chain, processing trigger (ECON-T) and data (ECON-D) streams from the HGCROC to the lpGBT. The ECONs will operate in a radiation environment with a High-Energy Hadron (${E\geq20MeV}$) flux up to $2\cdot10^{7} cm^{-2}s^{-1}$. This contribution describes the Universal Verification Methodology (UVM)-based functional verification of the ECON ASICs focusing on the re-use of existing components to manage the complexity of the verification environment.

physics.ins-det↗

arXiv2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

physics.ins-det↗

arXiv2022

A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.

physics.ins-det↗

arXiv2022

QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

physics.ins-det↗

arXiv2022

A 20 Gbps PAM4 Data Transmitter ASIC for Particle Physics Experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

physics.ins-det↗

arXiv2020

A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps

We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.

physics.ins-det↗

arXiv2020

A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.

physics.ins-det↗

arXiv2020

A 4-Channel 10-Gbps/ch CMOS VCSEL Array Driver with on-chip Charge-pumps

We present the design and test results of a 4-channel 10-Gbps/ch Vertical-Cavity Surface-Emitting Laser array driver, the cpVLAD. With on-chip charge-pumps to extend the biasing headroom for the VCSELs needed for low temperature operation and mitigation of the radiation effects. The cpVLAD was fabricated in a 65-nm CMOS technology. The test results show that the cpVLAD is capable of driving VCSELs with forward bias voltages as high as 2.8 V from a 2.5 V power supply. The power consumption of the cpVLAD is 94 mW/ch.

physics.ins-det↗

arXiv2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize them, retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

physics.ins-det↗

arXiv2019

EUDAQ $-$ A Data Acquisition Software Framework for Common Beam Telescopes

EUDAQ is a generic data acquisition software developed for use in conjunction with common beam telescopes at charged particle beam lines. Providing high-precision reference tracks for performance studies of new sensors, beam telescopes are essential for the research and development towards future detectors for high-energy physics. As beam time is a highly limited resource, EUDAQ has been designed with reliability and ease-of-use in mind. It enables flexible integration of different independent devices under test via their specific data acquisition systems into a top-level framework. EUDAQ controls all components globally, handles the data flow centrally and synchronises and records the data streams. Over the past decade, EUDAQ has been deployed as part of a wide range of successful test beam campaigns and detector development applications.

physics.ins-det↗

arXiv2019

Detector Technologies for CLIC

The Compact Linear Collider (CLIC) is a high-energy high-luminosity linear electron-positron collider under development. It is foreseen to be built and operated in three stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3 TeV, respectively. It offers a rich physics program including direct searches as well as the probing of new physics through a broad set of precision measurements of Standard Model processes, particularly in the Higgs-boson and top-quark sectors. The precision required for such measurements and the specific conditions imposed by the beam dimensions and time structure put strict requirements on the detector design and technology. This includes low-mass vertexing and tracking systems with small cells, highly granular imaging calorimeters, as well as a precise hit-time resolution and power-pulsed operation for all subsystems. A conceptual design for the CLIC detector system was published in 2012. Since then, ambitious R&D programmes for silicon vertex and tracking detectors, as well as for calorimeters have been pursued within the CLICdp, CALICE and FCAL collaborations, addressing the challenging detector requirements with innovative technologies. This report introduces the experimental environment and detector requirements at CLIC and reviews the current status and future plans for detector technology R&D.

physics.ins-det↗

arXiv2019

Tracking performance and simulation of capacitively coupled pixel detectors for the CLIC vertex detector

In order to achieve the challenging requirements on the CLIC vertex detector, a range of technology options have been considered in recent years. One prominent idea is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel readout chips. Recent results have shown the approach to be feasible, though more detailed studies of the performance of such devices, including simulation, are required. The CLICdp collaboration has developed a number of ASICs as part of its vertex detector R&D programme, and here we present results on the performance of a CCPDv3 active sensor glued to a CLICpix readout chip. Charge collection characteristics and tracking performance have been measured over the full expected angular range of incident particles using 120 GeV/c secondary hadron beams from the CERN SPS. Single hit efficiencies have been observed above 99% in the full range of track incidence angles, down to shallow angles. The single hit resolution has also been observed to be stable over this range, with a resolution around 6 $μ$m. The measured charge collection characterstics have been compared to simulations carried out using the Sentaurus TCAD finite-element simulation package combined with circuit simulations and parametrisations of the readout chip response. The simulations have also been successfully used to reproduce electric fields, depletion depths and the current-voltage characteristics of the device, and have been further used to make predictions about future device designs.

physics.ins-det↗

arXiv2017

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $μ$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $Ω$cm for the substrate and tested in standalone mode. The results show a rise time of $\sim20$ ns, charge gain of $190$ mV/ke$^{-}$ and $\sim40$ e$^{-}$ RMS noise for a power consumption of $4.8$ $μ$W/pixel. The main design aspects, as well as standalone measurement results, are presented.

physics.ins-det↗

arXiv2017

Higgs Physics at the CLIC Electron-Positron Linear Collider

The Compact Linear Collider (CLIC) is an option for a future e+e- collider operating at centre-of-mass energies up to 3 TeV, providing sensitivity to a wide range of new physics phenomena and precision physics measurements at the energy frontier. This paper is the first comprehensive presentation of the Higgs physics reach of CLIC operating at three energy stages: sqrt(s) = 350 GeV, 1.4 TeV and 3 TeV. The initial stage of operation allows the study of Higgs boson production in Higgsstrahlung (e+e- -> ZH) and WW-fusion (e+e- -> Hnunu), resulting in precise measurements of the production cross sections, the Higgs total decay width Gamma_H, and model-independent determinations of the Higgs couplings. Operation at sqrt(s) > 1 TeV provides high-statistics samples of Higgs bosons produced through WW-fusion, enabling tight constraints on the Higgs boson couplings. Studies of the rarer processes e+e- -> ttH and e+e- -> HHnunu allow measurements of the top Yukawa coupling and the Higgs boson self-coupling. This paper presents detailed studies of the precision achievable with Higgs measurements at CLIC and describes the interpretation of these measurements in a global fit.

hep-ex↗

arXiv2014

ECFA Detector R&D Panel, Review Report

Two special calorimeters are foreseen for the instrumentation of the very forward region of an ILC or CLIC detector; a luminometer (LumiCal) designed to measure the rate of low angle Bhabha scattering events with a precision better than 10$^{-3}$ at the ILC and 10$^{-2}$ at CLIC, and a low polar-angle calorimeter (BeamCal). The latter will be hit by a large amount of beamstrahlung remnants. The intensity and the spatial shape of these depositions will provide a fast luminosity estimate, as well as determination of beam parameters. The sensors of this calorimeter must be radiation-hard. Both devices will improve the e.m. hermeticity of the detector in the search for new particles. Finely segmented and very compact electromagnetic calorimeters will match these requirements. Due to the high occupancy, fast front-end electronics will be needed. Monte Carlo studies were performed to investigate the impact of beam-beam interactions and physics background processes on the luminosity measurement, and of beamstrahlung on the performance of BeamCal, as well as to optimise the design of both calorimeters. Dedicated sensors, front-end and ADC ASICs have been designed for the ILC and prototypes are available. Prototypes of sensor planes fully assembled with readout electronics have been studied in electron beams.

physics.ins-det↗

arXiv2011

Luminometer for the future International Linear Collider - simulation and beam test results

LumiCal will be the luminosity calorimeter for the proposed International Large Detector of the International Linear Collider (ILC). The ILC physics program requires the integrated luminosity to be measured with a relative precision on the order of 10e-3, or 10e-4 when running in GigaZ mode. Luminosity will be determined by counting Bhabha scattering events coincident in the two calorimeter modules placed symmetrically on opposite sides of the interaction point. To meet these goals, the energy resolution of the calorimeter must be better than 1.5% at high energies. LumiCal has been designed as a 30-layer sampling calorimeter with tungsten as the passive material and silicon as the active material. Monte Carlo simulation using the Geant4 software framework has been used to identify design elements which adversely impact energy resolution and correct for them without loss of statistics. BeamCal, covering polar angles smaller than LumiCal, will serve for beam tuning, luminosity optimisation and high energy electron detection. Secondly, prototypes of the sensors and electronics for both detectors have been evaluated during beam tests, the results of which are also presented here.

physics.ins-det↗