arXiv subjects

Salma Abdelzaher

Publications and source records attributed to Salma Abdelzaher.

4 recordsLinked to original sources

arXiv2026

Adaptive Inductor and Frequency Management for Integrated Power Converters

This work presents a digitally controlled adaptive power conversion framework that dynamically co-optimizes inductor configuration and switching frequency to achieve high efficiency across a wide range of load conditions. Conventional buck converters are typically optimized for a single operating point, leading to efficiency degradation under dynamic loads due to mismatches between inductance, switching frequency, and load current. To address this limitation, a reconfigurable inductor architecture is proposed. With this approach, the effective inductance and switching frequency are adjusted at runtime with on-chip digital controller. An end-to-end design methodology is developed, integrating physics-based analytical modeling, finite element method (FEM) simulations, and an optimization framework to determine preferred operating points across the load range. The resulting configurations are stored in a lookup table and implemented in real time through a low-overhead control scheme. The system explicitly accounts for both inductor and switching device losses, enabling co-optimization of conduction and switching losses within current ripple and continuous conduction mode (CCM) constraints. To ensure robust operation under fast load transients, a hysteresis-based control strategy is introduced to mitigate temporary CCM violations caused by sensing latency. An entry-margin condition is derived under which continuous conduction is guaranteed for a bounded load slew rate. Simulation results demonstrate a 4.5 percentage-point improvement in average efficiency and up to a 32% reduction in average power loss relative to fixed configurations, highlighting the effectiveness of adaptive inductance-frequency management in integrated power delivery systems with dynamic load profiles.

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arXiv2026

Electrothermal behavior of superconducting nanowires buried in a commercial CMOS process

Superconducting films native to a commercial CMOS process enable co-integration of superconducting devices (high-kinetic-inductance elements and nanowire detectors) with cryogenic CMOS on one monolithic die. Such films are buried in the front-end-of-line, beneath the back-end-of-line metal stack, an environment that might quench a self-heated hot spot. Current-voltage characteristics are reported for titanium nitride (TiN) nanowires in the polycrystalline-silicon resistor layer of a 22 nm FD-SOI process, and measured retrapping currents are compared with thermal models for longitudinal conduction to the contacts and interfacial phonon cooling into the stack. The wires are strongly hysteretic, with switching-to-retrapping current ratios I_sw/I_r of 7.4-9.8, sustaining a normal hot spot. For two wires of length ell = 50 micrometers and widths W = 0.50 and 1.00 micrometers, over bath temperatures T_b = 0.15-1.19 K, I_r follows the interfacial form (T_hs^n - T_b^n)^(1/2) with n = 4 (T_hs, the effective hot-spot temperature), and is strongly inconsistent with the (T_hs - T_b)^(1/2) constant-kappa longitudinal-conduction limit; free-exponent fits give n = approximately 4.8-5.0. An effective cooling coefficient Sigma_K = 7.9(3) W/(m^2 K^4) describes the data: 31(21) times below the acoustic- (diffuse-) mismatch value for a single clean interface, and approximately 12 times below the lowest previously reported comparable nanowire coefficient. The model-based film thermal conductivity is kappa = approximately 20 mW/(m K). Across lengths ell = 1-50 micrometers, I_r matches neither ell^(-1) of pure longitudinal conduction nor ell^0 of pure interfacial cooling; a two-channel model reproduces I_r(ell) with crossover length ell* = approximately 3.5 micrometers predicted, to an O(1) prefactor, from Sigma_K and kappa.

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arXiv2026

Package-Embedded Coupled Inductor Arrays for High-Performance Computing Power Delivery

A novel power delivery framework, comprising a package-embedded inductor topology and an inductance-island methodology, is introduced to maximize both inductance and current densities in vertical power delivery (VPD). The framework leverages multiple multi-phase converters, a common strategy in high-performance computing systems, to enhance efficiency and scalability. The proposed topology employs an array of tightly coupled spiral square inductors sharing a common magnetic rod, serving multiple converters operating in the same conversion phase. The array is optimized to maximize coupling and minimize conversion losses, achieving superior inductance and current densities of 250 nH/mm^2 and 10 A/mm^2, respectively. At the system level, the inductance-island methodology partitions the power delivery network into multiple islands, each dedicated to a converter phase and supplying a portion of the load current, thereby enabling scalable and efficient distribution. To validate the framework, the inductor array is designed and simulated in ANSYS Maxwell 3D and Mechanical, exhibiting an average quality factor of 23.6 and efficiency of 97.4% at 2 A load current, 6 V input, and 10 MHz switching frequency. The inductor array netlist is extracted from ANSYS and co-designed in Cadence Virtuoso with a distributed dual-phase power conversion system, ensuring joint optimization of passive and active components. The co-designed converter achieves a significant efficiency gain of 5.65% on average and up to 11.04% at 40 A load over a similar converter with uncoupled inductors, demonstrating the practical benefits of the approach.

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arXiv2025

A 28nm Multiply-Accumulate ASIC Architecture for On-Chip Data Compression in MHz Frame Rate X-ray and Electron Pixel Detectors

Modern X-ray detector systems urgently require compact, efficient, and fast data compression schemes to handle the transmission of big data from pixel arrays, enabling frame rates in the MHz regime. In this work, a data compression ASIC that implements a streaming fixed-length lossy compression scheme is introduced and analyzed, proving the feasibility and benefits of on-chip compression. The compression scheme utilizes a vector matrix product logic, which performs a number of floating-point multiplications, additions, and accumulations. The logic is verified, synthesized, and shown to fit in the area resource available for the X-ray detector under study, which comprises 192 x 168 pixels each of 12-bit width, and having a total area of 20 mm x 20 mm, about 2 mm x 20 mm of which are available for the digital logic. Several system architectures, precisions, and compression ratios ranging from 100 to 250 were analyzed to pave the way for on-chip fixed-length compression (e.g., principal component analysis, singular value decomposition) and data reduction (e.g., azimuthal integration) for X-ray and electron detectors.

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