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Sarit Dhar

Publications and source records attributed to Sarit Dhar.

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The completed High-Low method for interface state density analysis in MOS capacitors

Interface state densities, $D_{IT}$, in metal-oxide-semiconductor (MOS) capacitors are rarely reported in the accumulation energy range. It is recognized that the determination of $D_{IT}$ in accumulation is fundamentally obscured by small inaccuracies in the user-defined oxide capacitance, $C_{OX}$. This source of error prevents the High-Low frequency technique from reporting accumulation $D_{IT}$, even for sufficiently fast high-frequency measurements. To resolve this, an electrostatic constraint that is uniquely satisfied by a physically consistent $C_{OX}$ is derived from the established theory, thereby completing the High-Low framework. The "completed" framework's theoretical validity is confirmed using simulated capacitance data for an n-SiC MOS structure, and the method's frequency limitations are demonstrated. This analytical advancement ensures a physically consistent extraction of $D_{IT}$ near the band edge, overcoming a fundamental limitation in MOS capacitor characterization.

cond-mat.mtrl-sci

Atomic origin of high temperature electron trapping in MOS devices

MOSFETs based on wide band-gap semiconductors are suitable for operations at high temperature, at which additional atomic-scale processes that are benign at lower temperatures can get activated which results in device degradation. Recently significant enhancement of electron trapping was observed under positive bias in SiC MOSFETs at temperatures higher than 150°C. Here we report first-principle calculations showing that the enhanced electron trapping is associated with thermally activated capturing of a second electron by an oxygen vacancy in SiO2, by which the vacancy transforms into a new structure that comprises one Si dangling bond and a bond between a five-fold and a four-fold Si atoms. The results suggest a key role of oxygen vacancies and their structural reconfigurations in the reliability of high-temperature MOS devices.

cond-mat.mtrl-sci