arXiv subjects

Selçuk Köse

Publications and source records attributed to Selçuk Köse.

12 recordsLinked to original sources

arXiv2026

A 64-Spin All-to-All CMOS Ising Machine with Landscape Perturbation Achieving 2.28 nJ/Edge-Bit Energy-to-Solution

A 64-spin all-to-all current-mode coupling Ising machine is implemented in 65 nm CMOS. The design supports 31 coefficient levels in 0.943 mm2 and achieves Energy-to-Solution (ETS) of 2.28 nJ/edge-bit. Continuous programming refresh not only mitigates leakage but also provides a mechanism for deterministic energy landscape perturbation, which consistently improves solution quality with higher success rate compared to operation without landscape perturbation.

cs.AR↗

arXiv2026

Reed-Muller Error-Correction Code Encoder for SFQ-to-CMOS Interface Circuits

Data transmission from superconducting digital electronics such as single flux quantum (SFQ) logic to semiconductor (CMOS) circuits is subject to bit errors due to, e.g., flux trapping, process parameter variations (PPV), and fabrication defects. In this paper, a lightweight hardware-efficient error-correction code encoder is designed and analyzed. Particularly, a Reed-Muller code RM(1,3) encoder is implemented with SFQ digital logic. The proposed RM(1,3) encoder converts a 4-bit message into an 8-bit codeword and can detect and correct up to 3- and 1-bit errors, respectively. This encoder circuit is designed using MIT-LL SFQ5ee process and SuperTools/ColdFlux RSFQ cell library. A simulation framework integrating JoSIM simulator and MATLAB script for automated data collection and analysis, is proposed to study the performance of RM(1,3) encoder. The proposed encoder improves the probability of having no bit errors by 6.7% as compared to an encoder-less design under $\pm20\%$ PPV. With $\pm15\%$ and lower PPV, the proposed encoder could correct all errors with at least 99.1% probability. The impact of fabrication defects such as open circuit faults on the encoder circuit is also studied using the proposed framework.

eess.SP↗

arXiv2026

Interfacing Superconductor and Semiconductor Digital Electronics

Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.

physics.app-ph↗

arXiv2025

Lightweight Error-Correction Code Encoders in Superconducting Electronic Systems

Data transmission from superconducting electronic circuits, such as single flux quantum (SFQ) logic, to room-temperature electronics is susceptible to bit errors, which may result from flux trapping, fabrication defects, and process parameter variations (PPV). Due to the cooling power budget at 4.2 K and constraints on the chip area, the size of the error-correction code encoders is limited. In this work, three lightweight error-correction code encoders are proposed that are based on Hamming(7,4), Hamming(8,4), and Reed-Muller(1,3) codes and implemented with SFQ logic. The performance of these encoders is analyzed in the presence of PPV. The trade-offs between the theoretical complexity and physical size of error-correction code encoders are identified.

eess.SP↗

arXiv2025

MC3: Memory Contention based Covert Channel Communication on Shared DRAM System-on-Chips

Shared-memory system-on-chips (SM-SoC) are ubiquitously employed by a wide-range of mobile computing platforms, including edge/IoT devices, autonomous systems and smartphones. In SM-SoCs, system-wide shared physical memory enables a convenient and financially-feasible way to make data accessible by dozens of processing units (PUs), such as CPU cores and domain specific accelerators. In this study, we investigate vulnerabilities that stem from the shared use of physical memory in such systems. Due to the diverse computational characteristics of the PUs they embed, SM-SoCs often do not employ a shared last level cache (LLC). While the literature proposes covert channel attacks for shared memory systems, high-throughput communication is currently possible by either relying on an LLC or privileged/physical access to the shared memory subsystem. In this study, we introduce a new memory-contention based covert communication attack, MC3, which specifically targets the shared system memory in mobile SoCs. Different from existing attacks, our approach achieves high throughput communication between applications running on CPU and GPU without the need for an LLC or elevated access to the system. We extensively explore the effectiveness of our methodology by demonstrating the trade-off between the channel transmission rate and the robustness of the communication. We demonstrate the utility of MC3 on NVIDIA Orin AGX, Orin NX, and Orin Nano up to a transmit rate of 6.4 kbps with less than 1% error rate.

cs.CR↗

arXiv2024

A Pseudo-random Number Generator for Multi-Sequence Generation with Programmable Statistics

Pseudo-random number generators (PRNGs) are essential in a wide range of applications, from cryptography to statistical simulations and optimization algorithms. While uniform randomness is crucial for security-critical areas like cryptography, many domains, such as simulated annealing and CMOS-based Ising Machines, benefit from controlled or non-uniform randomness to enhance solution exploration and optimize performance. This paper presents a hardware PRNG that can simultaneously generate multiple uncorrelated sequences with programmable statistics tailored to specific application needs. Designed in 65nm process, the PRNG occupies an area of approximately 0.0013mm^2 and has an energy consumption of 0.57pJ/bit. Simulations confirm the PRNG's effectiveness in modulating the statistical distribution while demonstrating high-quality randomness properties.

cs.CR↗

arXiv2024

SKI-SAT: A CMOS-compatible Hardware for Solving SAT Problems

Nature-inspired computation is receiving increasing attention. Various Ising machine implementations have recently been proven to be effective in solving numerous combinatorial optimization problems including maximum cut, low density parity check (LDPC) decoding, and Boolean satisfiability (SAT) problems. In this paper, a novel method is presented to solve SAT or MAX-SAT problems with a CMOS circuit implementation. The technique solves a SAT problem by mapping the SAT variables onto quantized capacitor voltages generated by an array of nodes that interact through a network of coupling units. The nodal interaction is achieved through coupling currents produced by the coupling units, which charge or discharge capacitor voltages, implementing a gradient descent along the SAT problem's cost function to minimize the number of unsatisfied clauses. The system also incorporates a unique low-complexity perturbation scheme to avoid settling in local minima, greatly enhancing the performance of the system. The simulation results demonstrate that the proposed SKI-SAT is a high-performance and low-energy alternative that surpasses existing solvers by significant margins, achieving more than 10 times faster solution and 300 times less power.

cs.IT↗

arXiv2021

Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert Communication

Switched-capacitor (SC) DC-DC voltage converters are widely used in power delivery and management of modern integrated circuits. Connected to a common supply voltage, SC converters exhibit cross-regulation/coupling effects among loads connected to different SC converter stages due to the shared components such as switches, capacitors, and parasitic elements. The coupling effects between SC converter stages can potentially be used in covert communication, where two or more entities (e.g., loads) illegitimately establish a communication channel to exchange malicious information stealthily. To qualitatively analyze the coupling effects, a novel modeling technique is proposed based on the multi-port network theory. The fast and slow switching limit (FSL and SSL) equivalent resistance concepts are used to analytically determine the impact of each design parameter such as switch resistance, flying capacitance, switching frequency, and parasitic resistance. A three-stage 2:1 SC converter supplying three different loads is considered as a case study to verify the proposed modeling technique.

eess.SY↗

arXiv2020

Reducing Precoder/Channel Mismatch and Enhancing Secrecy in Practical MIMO Systems Using Artificial Signals

Practical multiple-input-multiple-output (MIMO) systems depend on a predefined set of precoders to provide spatial multiplexing gain. This limitation on the flexibility of the precoders affects the overall performance. Here, we propose a transmission scheme that can reduce the effect of mismatch between users' channels and precoders. The scheme uses the channel knowledge to generate an artificial signal, which realigns the predefined precoder to the actual channel. Moreover, the scheme can provide an additional level of secrecy for the communication link. The performance of the proposed scheme is evaluated using bit-error rate (BER), error vector magnitude (EVM), and secrecy capacity. The results show a significant improvement for the legitimate user, along with a degradation for the eavesdropper.

eess.SP↗

arXiv2020

Voltage regulator assisted lightweight countermeasure against fault injection attacks

The impeccable design of sensitive and cryptographic circuits (CC) against fault injection attacks is essential for modern data storage, communication, and computation systems that are susceptible to fault injection attacks. The robustness of a CC against voltage glitch attacks increases with an on-chip voltage regulator that considers the impact of topology and component selection on the fault injection robustness. With an emphasis on increasing the number of phases in a multiphase voltage regulator and component selection, an on-chip voltage regulator with multiphase configuration and an optimal operating point is proposed as a lightweight countermeasure to minimize injected glitches. Furthermore, an infective countermeasure is added to the on-chip multiphase voltage regulator that contaminates the computation of the cryptographic algorithm when a voltage glitch reaches to the CC. By increasing the number of phases from 1 to 16, the confrontation with fault attacks increases by 52.45%, which is equal to 91.82% if the number of phases increases to 32. Using the infective countermeasure for fault resiliency, the security-enhanced CC provides a robust and resilient solution against fault attacks that improve the security and availability of the device.

cs.CR↗

arXiv2019

Extensionless Adaptive Transmitter and Receiver Windowing of Beyond 5G Frames

Newer cellular communication generations are planned to allow asynchronous transmission of multiple numerologies (waveforms with different parameters) in adjacent bands, creating unavoidable adjacent channel interference. Most prior work on windowing assume additional extensions reserved for windowing, which does not comply with standards. Whether windowing should be applied at the transmitter or the receiver was not questioned. In this work, we propose two independent algorithms that are implemented at the transmitter and receiver, respectively. These algorithms estimate the transmitter and receiver windowing duration of each resource element (RE) with an aim to improve fair proportional network throughput. While doing so, we solely utilize the available extension that was defined in the standard and present standard-compliant algorithms that also do not require any modifications on the counterparts or control signaling. Furthermore, computationally efficient techniques to apply per-RE transmitter and receiver windowing to signals synthesized and analyzed using conventional cyclic prefix orthogonal frequency division multiplexing are derived and their computational complexities are analyzed. The spectrotemporal relations between optimum window durations at either side, as well as functions of the excess signal to noise ratios, the subcarrier spacings and the throughput gains provided over previous similar techniques are numerically verified.

eess.SP↗

arXiv2019

Innovative Telecommunications Training through Flexible Radio Platforms

The ever-changing telecommunication industry is in severe need of a highly-skilled workforce to shape and deploy future generation communication systems. This article presents an innovative telecommunication training that is designed to satisfy this need. The training focuses on hardware layers of the open systems interconnection model. It integrates theory, numerical modeling, and hardware implementation to ensure a complete and long-lasting understanding. The key telecommunication concepts that are covered in the fundamental training phase are detailed along with best teaching practices. In addition, the methods that enrich the learning experience, such as gamified micro-tasks and interactive use of daily telecommunication devices, are featured. The project development case studies that cultivate creative thinking and scientific interest are highlighted. Also, a well-established guideline to compose the teaching environment that emphasizes hands-on experience is provided. Therefore, the presented training can be exemplary to other institutions that share the same mission to educate the distinguished engineers of the future.

eess.SP↗