arXiv subjects

Susmita Sur-Kolay

Publications and source records attributed to Susmita Sur-Kolay.

At least 37 records · Page 2Linked to original sources

arXiv2022

$i$-QER: An Intelligent Approach towards Quantum Error Reduction

Quantum computing has become a promising computing approach because of its capability to solve certain problems, exponentially faster than classical computers. A $n$-qubit quantum system is capable of providing $2^{n}$ computational space to a quantum algorithm. However, quantum computers are prone to errors. Quantum circuits that can reliably run on today's Noisy Intermediate-Scale Quantum (NISQ) devices are not only limited by their qubit counts but also by their noisy gate operations. In this paper, we have introduced $i$-QER, a scalable machine learning-based approach to evaluate errors in a quantum circuit and helps to reduce these without using any additional quantum resources. The $i$-QER predicts possible errors in a given quantum circuit using supervised learning models. If the predicted error is above a pre-specified threshold, it cuts the large quantum circuit into two smaller sub-circuits using an error-influenced fragmentation strategy for the first time to the best of our knowledge. The proposed fragmentation process is iterated until the predicted error reaches below the threshold for each sub-circuit. The sub-circuits are then executed on a quantum device. Classical reconstruction of the outputs obtained from the sub-circuits can generate the output of the complete circuit. Thus, $i$-QER also provides classical control over a scalable hybrid computing approach, which is a combination of quantum and classical computers. The $i$-QER tool is available at https://github.com/SaikatBasu90/i-QER.

quant-ph↗

arXiv2021

FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs

High-level synthesis (HLS) is the next emerging trend for designing complex customized architectures for applications such as Machine Learning, Video Processing. It provides a higher level of abstraction and freedom to hardware engineers to perform hardware software co-design. However, it opens up a new gateway to attackers to insert hardware trojans. Such trojans are semantically more meaningful and stealthy, compared to gate-level trojans and therefore are hard-to-detect using state-of-the-art gate-level trojan detection techniques. Although recent works have proposed detection mechanisms to uncover such stealthy trojans in high-level synthesis (HLS) designs, these techniques are either specially curated for existing trojan benchmarks or may run into scalability issues for large designs. In this work, we leverage the power of greybox fuzzing combined with concolic execution to explore deeper segments of design and uncover stealthy trojans. Experimental results show that our proposed framework is able to automatically detect trojans faster with fewer test cases, while attaining notable branch coverage, without any manual pre-processing analysis.

cs.CR↗

arXiv2021

Efficient Decoding of Surface Code Syndromes for Error Correction in Quantum Computing

Errors in surface code have typically been decoded by Minimum Weight Perfect Matching (MWPM) based method. Recently, neural-network-based Machine Learning (ML) techniques have been employed for this purpose. Here we propose a two-level (low and high) ML-based decoding scheme, where the first level corrects errors on physical qubits and the second one corrects any existing logical errors, for different noise models. Our results show that our proposed decoding method achieves $\sim10 \times$ and $\sim2 \times$ higher values of pseudo-threshold and threshold respectively, than for MWPM. We show that usage of more sophisticated ML models with higher training/testing time, do not provide significant improvement in the decoder performance. Finally, data generation for training the ML decoder requires significant overhead hence lower volume of training data is desirable. We have shown that our decoder maintains a good performance with the train-test-ratio as low as $40:60$.

quant-ph↗

arXiv2021

Depth Optimized Ansatz Circuit in QAOA for Max-Cut

While a Quantum Approximate Optimization Algorithm (QAOA) is intended to provide a quantum advantage in finding approximate solutions to combinatorial optimization problems, noise in the system is a hurdle in exploiting its full potential. Several error mitigation techniques have been studied to lessen the effect of noise on this algorithm. Recently, Majumdar et al. proposed a Depth First Search (DFS) based method to reduce $n-1$ CNOT gates in the ansatz design of QAOA for finding Max-Cut in a graph G = (V, E), |V| = n. However, this method tends to increase the depth of the circuit, making it more prone to relaxation error. The depth of the circuit is proportional to the height of the DFS tree, which can be $n-1$ in the worst case. In this paper, we propose an $O(Δ\cdot n^2)$ greedy heuristic algorithm, where $Δ$ is the maximum degree of the graph, that finds a spanning tree of lower height, thus reducing the overall depth of the circuit while still retaining the $n-1$ reduction in the number of CNOT gates needed in the ansatz. We numerically show that this algorithm achieves nearly 10 times increase in the probability of success for each iteration of QAOA for Max-Cut. We further show that although the average depth of the circuit produced by this heuristic algorithm still grows linearly with n, our algorithm reduces the slope of the linear increase from 1 to 0.11.

quant-ph↗

arXiv2021

Faster Search of Clustered Marked States with Lackadaisical Quantum Walks

The nature of discrete-time quantum walk in the presence of multiple marked states has been studied by Nahimovs and Rivosh. They introduced an exceptional configuration of clustered marked states $i.e.,$ if the marked states are arranged in a $\sqrt{k} \times \sqrt{k}$ cluster within a $\sqrt{N} \times \sqrt{N}$ grid, where $k=n^{2}$ and $n$ an odd integer. They showed that finding a single marked state among the multiple ones using quantum walk with AKR (Ambainis, Kempe and Rivosh) coin requires $Ω(\sqrt{N} - \sqrt{k})$ time. Furthermore, Nahimov and Rivosh also showed that the Grover's coin can find the same configuration of marked state both faster and with higher probability compared to that with the AKR coin. In this article, we show that using lackadaisical quantum walk, a variant of a three-state discrete-time quantum walk on a line, the success probability of finding all the clustered marked states of this exceptional configuration is nearly 1 with smaller run-time. We also show that the weights of the self-loop suggested for multiple marked states in the state-of-the-art works are not optimal for this exceptional configuration of clustered mark states. We propose a range of weights of the self-loop from which only one can give the desired result for this configuration.

quant-ph↗

arXiv2021

Optimizing Ansatz Design in QAOA for Max-cut

Quantum Approximate Optimization Algorithm (QAOA) is studied primarily to find approximate solutions to combinatorial optimization problems. For a graph with $n$ vertices and $m$ edges, a depth $p$ QAOA for the Max-cut problem requires $2\cdot m \cdot p$ CNOT gates. CNOT is one of the primary sources of error in modern quantum computers. In this paper, we propose two hardware independent methods to reduce the number of CNOT gates in the circuit. First, we present a method based on Edge Coloring of the input graph that minimizes the the number of cycles (termed as depth of the circuit), and reduces upto $\lfloor \frac{n}{2} \rfloor$ CNOT gates. Next, we depict another method based on Depth First Search (DFS) on the input graph that reduces $n-1$ CNOT gates, but increases depth of the circuit moderately. We analytically derive the condition for which the reduction in CNOT gates overshadows this increase in depth, and the error probability of the circuit is still lowered. We show that all IBM Quantum Hardware satisfy this condition. We simulate these two methods for graphs of various sparsity with the \textit{ibmq\_manhattan} noise model, and show that the DFS based method outperforms the edge coloring based method, which in turn, outperforms the traditional QAOA circuit in terms of reduction in the number of CNOT gates, and hence the probability of error of the circuit.

quant-ph↗

arXiv2020

Exploiting degeneracy to construct good ternary quantum error correcting code

Quantum error-correcting code for higher dimensional systems can, in general, be directly constructed from the codes for qubit systems. What remains unknown is whether there exist efficient code design techniques for higher dimensional systems. In this paper, we propose a 7-qutrit error-correcting code for the ternary quantum system and show that this design formulation has no equivalence in qubit systems. This code is optimum in the number of qutrits required to correct a single error while maintaining the CSS structure. This degenerate CSS code can (i) correct up to seven simultaneous phase errors and a single bit error, (ii) correct two simultaneous bit errors on pre-defined pairs of qutrits on eighteen out of twenty-one possible pairs, and (iii) in terms of the cost of implementation, the depth of the circuit of this code is only two more than that of the ternary Steane code. Our proposed code shows that it is possible to design better codes explicitly for ternary quantum systems instead of simply carrying over codes from binary quantum systems.

quant-ph↗

arXiv2020

STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction

With aggressively shrinking process nodes, physical design methods face severe challenges due to poor convergence and uncertainty in getting an optimal solution. An early detection of potential failures is thus mandated. This has encouraged to devise a feedback mechanism from a lower abstraction level of the design flow to the higher ones, such as placement driven synthesis, routability (timing) driven placement etc. Motivated by this, we propose an early global routing framework using pattern routing following the floorplanning stage. We assess feasibility of a floorplan topology of a given design by estimating routability, routed wirelength and vias count while addressing the global congestion scenario across the layout. Different capacity profiles for the routing regions, such as uniform or non-uniform different cases of metal pitch variation across the metals layers ensures adaptability to technology scaling. The proposed algorithm STAIRoute takes $O(n^2kt)$ time for a given design with $n$ blocks and $k$ nets having at most $t$ terminals. Experimental results on a set of floorplanning benchmark circuits show $100\%$ routing completion, with no over-congestion in the routing regions reported. The wirelength for the $t$-terminal ($t\geq$ 2) nets is comparable with the Steiner length computed by FLUTE. An estimation on the number of vias for different capacity profiles is also presented, along with congestion and runtime results.

cs.OH↗

arXiv2020

Optimal Error Correcting Code For Ternary Quantum Systems

Multi-valued quantum systems can store more information than binary ones for a given number of quantum states. For reliable operation of multi-valued quantum systems, error correction is mandated. In this paper, we propose a 5-qutrit quantum error-correcting code and provide its stabilizer formulation. Since 5 qutrits are necessary to correct a single error, our proposed code is optimal in the number of qutrits. We prove that the error model considered in this paper spans the entire $(3 \times 3)$ operator space. Therefore, our proposed code can correct any single error on the codeword. This code outperforms the previous 9-qutrit code in (i) the number of qutrits required for encoding, (ii) our code can correct any arbitrary $(3 \times 3)$ error, (ii) our code can readily correct bit errors in a single step as opposed to the two-step correction used previously, and (iii) phase error correction does not require correcting individual subspaces.

quant-ph↗

arXiv2019

Minimal degenerate CSS quantum code with low cost circuit

Error correction is of utmost necessity for large-scale quantum computing. Quantum error correcting codes can be degenerate, if more than one type of error can map the input state to the same error state. In this paper, we propose a 6-qubit degenerate CSS code. We show that our proposed code can correct a single bit flip error, but arbitrarily many phase flip errors occurring on the codeword. Furthermore, it follows from a bound on CSS codes that the proposed code is the minimal binary CSS code which can encode a single qubit of information. We also perform a comparative study of the gate count required for a fault tolerant decomposition of the error correction circuit for the proposed code, with that for the existing 9-qubit, 7-qubit and 5-qubit binary QEC codes. Our results show, on an average over the different technologies a savings of 98.14% in the gate count for the proposed code over that for the 5-qubit code. Significant improvement of around 50% in gate count is also obtained when compared to those for the 9-qubit and 7-qubit codes.

quant-ph↗

arXiv2019

Quantum error correction for non-maximally entangled states

Quantum states have high affinity for errors and hence error correction is of utmost importance to realise a quantum computer. Laflamme showed that 5 qubits are necessary to correct a single error on a qubit. In a Pauli error model, four different types of errors can occur on a qubit. Maximally entangled states are orthogonal to each other and hence can be uniquely distinguished by a measurement in the Bell basis. Thus a measurement in Bell basis and a unitary transformation is sufficient to correct error in Bell states. However, such a measurement is not possible for non-maximally entangled states. In this work we show that the 16 possible errors for a non-maximally entangled two qubit system map to only 8 distinct error states. Hence, it is possible to correct the error without perfect knowledge of the type of error. Furthermore, we show that the possible errors can be grouped in such a way that all 4 errors can occur on one qubit, whereas only bit flip error can occur on the second qubit. As a consequence, instead of 10, only 8 qubits are sufficient to correct a single error. We propose an 8-qubit error correcting code to correct a single error in a non-maximally entangled state. We further argue that for an $n$-qubit non-maximally entangled state of the form $a|0>^{n} + b|1>^{n}$, it is always possible to correct a single error with fewer than $5n$ qubits, in fact only $3n+2$ qubits suffice.

quant-ph↗

arXiv2018

Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning

Random via failure is a major concern for post-fabrication reliability and poor manufacturing yield. A demanding solution to this problem is redundant via insertion during post-routing optimization. It becomes very critical when a multi-layer routing solution already incurs a large number of vias. Very few global routers addressed unconstrained via minimization (UVM) problem, while using minimal pattern routing and layer assignment of nets. It also includes a recent floorplan based early global routability assessment tool STAIRoute \cite{karb2}. This work addresses an early version of unconstrained via minimization problem during early global routing by identifying a set of minimal bend routing regions in any floorplan, by a new recursive bipartitioning framework. These regions facilitate monotone pattern routing of a set of nets in the floorplan by STAIRoute. The area/number balanced floorplan bipartitionining is a multi-objective optimization problem and known to be NP-hard \cite{majum2}. No existing approaches considered bend minimization as an objective and some of them incurred higher runtime overhead. In this paper, we present a Greedy as well as randomized neighbor search based staircase wave-front propagation methods for obtaining optimal bipartitioning results for minimal bend routing through multiple routing layers, for a balanced trade-off between routability, wirelength and congestion. Experiments were conducted on MCNC/GSRC floorplanning benchmarks for studying the variation of early via count obtained by STAIRoute for different values of the trade-off parameters ($γ, β$) in this multi-objective optimization problem, using $8$ metal layers. We studied the impact of ($γ, β$) values on each of the objectives as well as their linear combination function $Gain$ of these objectives.

cs.OH↗

arXiv2018

Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model

Multiple design iterations are inevitable in nanometer Integrated Circuit (IC) design flow until desired printability and performance metrics are achieved. This starts with placement optimization aimed at improving routability, wirelength, congestion and timing in the design. Contrarily, no such practice exists on a floorplanned layout, during the early stage of the design flow. Recently, STAIRoute \cite{karb2} aimed to address that by identifying the shortest routing path of a net through a set of routing regions in the floorplan in multiple metal layers. Since the blocks in hierarchical ASIC/SoC designs do not use all the permissible routing layers for the internal routing corresponding to standard cell connectivity, the proposed STAIRoute framework is not an effective for early global routability assessment. This leads to improper utilization of routing area, specifically in higher routing layers with fewer routing blockages, as the lack of placement of standard cells does not facilitates any routing of their interconnections. This paper presents a generalized model for early global routability assessment, HGR, by utilizing the free regions over the blocks beyond certain metal layers. The proposed (hybrid) routing model comprises of (a) the junction graph model in STAIRoute routing through the block boundary regions in lower routing layers, and (ii) the grid graph model for routing in higher layers over the free regions of the blocks. Experiment with the latest floorplanning benchmarks exhibit an average reduction of $4\%$, $54\%$ and $70\%$ in netlength, via count, and congestion respectively when HGR is used over STAIRoute. Further, we conducted another experiment on an industrial design flow targeted for $45nm$ process, and the results are encouraging with $~3$X runtime boost when early global routing is used in conjunction with the existing physical design flow.

cs.OH↗

arXiv2018

Search of clustered marked states with lackadaisical quantum walks

Nature of quantum walk in presence of multiple marked state has been studied by Nahimovs and Rivosh \cite{10.1007/978-3-662-49192-8_31}. They have shown that if the marked states are arranged in a $\sqrt{k} \times \sqrt{k}$ cluster in a $\sqrt{N} \times \sqrt{N}$ grid, then to find a single marked state among the multiple ones, quantum walk requires $Ω(\sqrt{N} - \sqrt{k})$ time. In this paper, we show that using lackadaisical quantum walk with the weight of the self-loop as $\frac{4}{N(k + \lfloor{\frac{\sqrt{k}}{2}}\rfloor)}$, where $k$ is odd, the probability of finding a marked state increases by $\sim 0.2$. Furthermore, we show that instead of applying the quantum walk $\mathcal{O}(k)$ times to find all the marked states, classical search in the vicinity of the marked state found after the first implementation of the quantum walk can find all the marked states in $\mathcal{O}(\sqrt{k})$ time on average.

quant-ph↗

arXiv2018

Quantum error-correcting code for ternary logic

Ternary quantum systems are being studied because these provide more computational state space per unit of information, known as qutrit. A qutrit has three basis states, thus a qubit may be considered as a special case of a qutrit where the coefficient of one of the basis states is zero. Hence both $(2 \times 2)$-dimensional as well as $(3 \times 3)$-dimensional Pauli errors can occur on qutrits. In this paper, we (i) explore the possible $(2 \times 2)$-dimensional as well as $(3 \times 3)$-dimensional Pauli errors in qutrits and show that any pairwise bit swap error can be expressed as a linear combination of shift errors and phase errors, (ii) propose a new type of error called quantum superposition error and show its equivalence to arbitrary rotation, (iii) formulate a nine qutrit code which can correct a single error in a qutrit, and (iv) provide its stabilizer and circuit realization.

quant-ph↗

arXiv2016

Error tracing in linear and concatenated quantum circuits

Descriptions of quantum algorithms, communication etc. protocols assume the existence of closed quantum system. However, real life quantum systems are open and are highly sensitive to errors. Hence error correction is of utmost importance if quantum computation is to be carried out in reality. Ideally, an error correction block should be placed after every gate operation in a quantum circuit. This increases the overhead and reduced the speedup of the quantum circuit. Moreover, the error correction blocks themselves may induce errors as the gates used for error correction may be noisy. In this paper, we have proposed a procedure to trace error probability due to noisy gates and decoherence in quantum circuit and place an error correcting block only when the error probability exceeds a certain threshold. This procedure shows a drastic reduction in the required number of error correcting blocks. Furthermore, we have considered concatenated codes with tile structure layout lattice architecture[25][21],[24] and SWAP gate based qubit transport mechanism. Tracing errors in higher levels of concatenation shows that, in most cases, after 1 or 2 levels of concatenation, the number of QECC blocks required become static. However, since the gate count increases with increasing concatenation, the percentage saving in gate count is considerably high.

quant-ph↗

arXiv2012

Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning

Linear Nearest Neighbor (LNN) synthesis in reversible circuits has emerged as an important issue in terms of technological implementation for quantum computation. The objective is to obtain a LNN architecture with minimum gate cost. As achieving optimal synthesis is a hard problem, heuristic methods have been proposed in recent literature. In this work we present a graph partitioning based approach for LNN synthesis with reduction in circuit cost. In particular, the number of SWAP gates required to convert a given gate-level quantum circuit to its equivalent LNN configuration is minimized. Our algorithm determines the reordering of indices of the qubit line(s) for both single control and multiple controlled gates. Experimental results for placing the target qubits of Multiple Controlled Toffoli (MCT) library of benchmark circuits show a significant reduction in gate count and quantum gate cost compared to those of related research works.

cs.ET↗

arXiv2012

A Synthesis Method for Quaternary Quantum Logic Circuits

Synthesis of quaternary quantum circuits involves basic quaternary gates and logic operations in the quaternary quantum domain. In this paper, we propose new projection operations and quaternary logic gates for synthesizing quaternary logic functions. We also demonstrate the realization of the proposed gates using basic quantum quaternary operations. We then employ our synthesis method to design of quaternary adder and some benchmark circuits. Our results in terms of circuit cost, are better than the existing works.

cs.OH↗