arXiv subjects

Umamaheswara Rao Tida

Publications and source records attributed to Umamaheswara Rao Tida.

9 recordsLinked to original sources

arXiv2026

AgentDV: Closed-Loop Agentic AI for Hardware Design Verification

Register-transfer level (RTL) verification consumes a major part of modern system-on-chip (SoC) development effort. Yet, recent LLM-based verification-code generation often fails to produce runnable, design-consistent, and coverage-producing testbenches. We present AgentDV, a closed-loop agentic AI framework for automated RTL verification environment generation. AgentDV transforms single-shot LLM testbench generation into a tool-grounded verification pipeline by combining LLM-guided analysis, testbench construction, simulation, coverage measurement, and iterative refinement. The framework introduces three key ideas: 1) runnability filtering to reject invalid generated environments, 2) CSR-grounded checking to reduce hallucinated signals and incorrect expected behavior, and 3) coverage-guided iteration to regenerate tests based on measured verification gaps. We evaluate AgentDV using three LLMs on challenge DUTs and public OpenTitan peripheral and security IP blocks. From our analysis, we observed that direct single-shot prompting fails to produce a valid coverage-producing environment on benchmarks. AgentDV achieves 100% pass rate on four DUTs and an average of 80.9% pass rate on all DUTs using Claude Sonnet 4.6. Similarly, an average of 58.7% and 60.6% pass rate is achieved for Llama and Qwen models, respectively. In addition, an average of 74.5%, 69.1%, and 64.9% of line coverage and 88.4%, 82.3%, and 76.7% of branch coverage for the benchmarks under consideration for Claude Sonnet 4.6, Llama, and Qwen models, respectively.

cs.SE↗

arXiv2026

SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design

Recent advances in large language models (LLMs) have demonstrated strong potential in generating hardware designs using hardware description languages (HDLs) such as Verilog. However, existing LLM-based frameworks struggle to accurately capture the complexity of real-world architectural designs, particularly for large-scale systems with hierarchical, multi-level module instantiations. To address this issue, we present SysVCoder, an LLM-driven framework that enhances both the generation quality and efficiency of system-level design in Verilog. SysVCoder introduces a two-stage generation pipeline that leverages an intermediate representation to enable a more structured and accurate translation from natural language specifications to complex multi-module designs. Furthermore, we incorporate a rule-based alignment mechanism and a domain-specific retrieval-augmented generation strategy (DS-RAG) to enhance functional correctness by grounding LLM outputs in domain knowledge. We also present SysVDB, a comprehensive dataset comprising 60 system-level hardware designs along with their corresponding verification testbenches. Experimental results demonstrate that SysVCoder outperforms state-of-the-art frameworks such as CodeV and VeriGen by 30.7% and 38.3% in terms of functional correctness under the same base LLM. Notably, SysVCoder achieves performance comparable to NVIDIA's GPT-4 based VerilogCoder while using only a 7B-parameter model, reducing token consumption by 7.6x and synthesis latency by 37.5x. Both SysVCoder and SysVDB are made public at https://gitee.com/sdu-aes-lab/sysvcoder/.

cs.SE↗

arXiv2026

LLM-as-Judge Framework for Evaluating Tone-Induced Hallucination in Vision-Language Models

Vision-Language Models (VLMs) are increasingly deployed in settings where reliable visual grounding carries operational consequences, yet their behavior under progressively coercive prompt phrasing remains undercharacterized. Existing hallucination benchmarks predominantly rely on neutral prompts and binary detection, leaving open how both the incidence and the intensity of fabrication respond to graded linguistic pressure across structurally distinct task types. We present Ghost-100, a procedurally constructed benchmark of 800 synthetically generated images spanning eight categories across three task families: text-illegibility, time-reading, and object-absence, each designed under a negative-ground-truth principle that guarantees the queried target is absent, illegible, or indeterminate by construction. Every image is paired with five prompts drawn from a structured 5-Level Prompt Intensity Framework, holding the image and task identity fixed while varying only directive force, so that tone is isolated as the sole independent variable. We adopt a dual-track evaluation protocol: a rule-based H-Rate measuring the proportion of responses in which a model crosses from grounded refusal into unsupported positive commitment, and a GPT-4o-mini-judged H-Score on a 1-5 scale characterizing the confidence and specificity of fabrication once it occurs. We additionally release a three-stage automated validation workflow, which retrospectively confirms 717 of 800 images as strictly compliant. Evaluating nine open-weight VLMs, we find that H-Rate and H-Score dissociate substantially across model families, reading-style and presence-detection subsets respond to prompt pressure in qualitatively different ways, and several models exhibit non-monotonic sensitivity peaking at intermediate tone levels: patterns that aggregate metrics obscure.

cs.CV↗

arXiv2026

Toward Accountable AI-Generated Content on Social Platforms: Steganographic Attribution and Multimodal Harm Detection

The rapid growth of generative AI has introduced new challenges in content moderation and digital forensics. In particular, benign AI-generated images can be paired with harmful or misleading text, creating difficult-to-detect misuse. This contextual misuse undermines the traditional moderation framework and complicates attribution, as synthetic images typically lack persistent metadata or device signatures. We introduce a steganography enabled attribution framework that embeds cryptographically signed identifiers into images at creation time and uses multimodal harmful content detection as a trigger for attribution verification. Our system evaluates five watermarking methods across spatial, frequency, and wavelet domains. It also integrates a CLIP-based fusion model for multimodal harmful-content detection. Experiments demonstrate that spread-spectrum watermarking, especially in the wavelet domain, provides strong robustness under blur distortions, and our multimodal fusion detector achieves an AUC-ROC of 0.99, enabling reliable cross-modal attribution verification. These components form an end-to-end forensic pipeline that enables reliable tracing of harmful deployments of AI-generated imagery, supporting accountability in modern synthetic media environments. Our code is available at GitHub: https://github.com/bli1/steganography

cs.CV↗

arXiv2026

CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval

Deploying Retrieval-Augmented Generation (RAG) on edge devices is in high demand, but is hindered by the latency of massive data movement and computation on traditional architectures. Compute-in-Memory (CiM) architectures address this bottleneck by performing vector search directly within their crossbar structure. However, CiM's adoption for RAG is limited by a fundamental ``representation gap,'' as high-precision, high-dimension embeddings are incompatible with CiM's low-precision, low-dimension array constraints. This gap is compounded by the diversity of CiM implementations (e.g., SRAM, ReRAM, FeFET), each with unique designs (e.g., 2-bit cells, 512x512 arrays). Consequently, RAG data must be naively reshaped to fit each target implementation. Current data shaping methods handle dimension and precision disjointly, which degrades data fidelity. This not only negates the advantages of CiM for RAG but also confuses hardware designers, making it unclear if a failure is due to the circuit design or the degraded input data. As a result, CiM adoption remains limited. In this paper, we introduce CQ-CiM, a unified, hardware-aware data shaping framework that jointly learns Compression and Quantization to produce CiM-compatible low-bit embeddings for diverse CiM designs. To the best of our knowledge, this is the first work to shape data for comprehensive CiM usage on RAG.

cs.ET↗

arXiv2023

FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration

Monolithic Three-Dimensional Integrated Circuits (M3D-IC) has become an attractive option to increase the transistor density. In M3D-IC, substrate layers are realized on top of previous layers using sequential integration techniques. Recent works in M3D-IC have demonstrated the feasibility of FDSOI process-based M3D-IC implementations and, Metal inter-layer vias (MIVs) are used to provide connections between the inter-layer devices. Since MIVs are extended from bottom layer to top layer, they occupy a small area resulting in area overhead. Additionally, a minimum separation is required to facilitate connection between MIV and transistors which increases this overhead further. Towards this, we studied the alternate utilization of MIV to create MIV-transistors with varying channels. We have also presented a strategy to extract the Spice parameters of the proposed models using level 70 spice parameters. Finally, a standard cell based gate level comparison is presented to compare the Power, Performance and Area (PPA) metrics of the traditional two layer 2D FDSOI transistor implementation with the proposed models. Simulation results from standard cell designs suggest that the proposed methodology can reduce 18\% layout area on average compared to the traditional approach. In addition, power consumption and delay time of the standard cells are reduced by 1\% and 3\% on average respectively.

eess.SY↗

arXiv2023

Efficient and Scalable MIV-transistor with Extended Gate in Monolithic 3D Integration

Monolithic 3D integration has become a promising solution for future computing needs. The metal inter-layer via (MIV) forms interconnects between substrate layers in Monolithic 3D integration. Despite small size of MIV, the area overhead can become a major limitation for efficient M3D integration and, thus needs to be addressed. Previous works focused on the utilization of the substrate area around MIV to reduce this area overhead significantly but suffers from increased leakage and scaling factors. In this work, we discuss MIV-transistor realization that addresses both leakage and scaling issue along with similar area overhead reduction compared with previous works and, thus can be utilized efficiently. Our simulation results suggest that the leakage current $(I_{D,leak})$ has reduced by $14K\times$ and, the maximum current $(I_{D,max})$ increased by $58\%$ for the proposed MIV-transistor compared with the previous implementation. In addition, performance metrics of the inverter realization with our proposed MIV-transistor specifically the delay, slew time and power consumption reduced by $11.6\%$, $17.9\%$ and, $4.5\%$ respectively compared with the previous implementation with same MIV area overhead reduction.

eess.SY↗

arXiv2023

Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration

Metal inter-layer via (MIV) in Monolithic three-dimensional integrated circuits (M3D-IC) is used to connect inter-layer devices and provide power and clock signals across multiple layers. The size of MIV is comparable to logic gates because of the significant reduction in substrate layers due to sequential integration. Despite MIV's small size, the impact of MIV on the performance of adjacent devices should be considered to implement IC designs in M3D-IC technology. In this work, we systematically study the changes in performance of transistors when they are placed near MIV to understand the effect of MIV on adjacent devices when MIV passes through the substrate. Simulation results suggest that the keep-out-zone (KOZ) for MIV should be considered to ensure the reliability of M3D-IC technology and this KOZ is highly dependent on the M3D-IC process. In this paper, we show that the transistor placed near MIV considering the M1 metal pitch as the separation will have up to $68,668\times$ increase in leakage current, when the channel doping is $10^{15} cm^{-3}$, source/drain doping of $10^{18}cm^{-3}$ and substrate layer height of $100\ nm$. We also show that, this increase in leakage current can also be reduced significantly by having KOZ around MIV, which is dependent on the process.

eess.SY↗

arXiv2020

An Improved Quadrature Voltage-Controlled Oscillator with Through-Silicon-Via Inductor in Three-dimensional Integrated Circuits

Low-power quadrature voltage-controlled oscillator (QVCO) design utilizing transformer-feedback and current-reuse techniques with increased frequency range is proposed in this paper. With increasing demand for QVCOs in on-chip applications, the conventional spiral inductor based approaches for QVCOs has become a major bottleneck due to their large size. To address this concern, we propose to replace the conventional spiral inductor based approaches with through-silicon-via (TSV) inductor based approach in three-dimensional integrated circuits (3D ICs). In addition, the proposed QVCO circuit can provide higher frequency range of operation compared with conventional designs. Experimental results show by replacing conventional spiral transformers with TSV transformers, up to 3.9x reduction in metal resource consumption. The proposed QVCOs achieves a phase noise of -114 $dBc/Hz$@1 $MHz$ and -111.2 $dBc/Hz$@1 $MHz$ at the carrier of 2.5 $GHz$ for toroidal TSV transformed based-QVCO and vertical spiral transformer based-QVCO respectively. The power consumption is only 1.5 $mW$ and 1.7 $mW$ for toroidal TSV transformed based-QVCO and vertical spiral transformer based-QVCO respectively, under the supply voltage of 0.7 $V$.

eess.SY↗