arXiv subjects

Wolfgang Lechner

Publications and source records attributed to Wolfgang Lechner.

At least 37 records · Page 2Linked to original sources

arXiv2025

Connectivity-aware Synthesis of Quantum Algorithms

We present a general method for the implementation of quantum algorithms that optimizes both gate count and circuit depth. Our approach introduces connectivity-adapted CNOT-based building blocks called Parity Twine chains. It outperforms all known state-of-the art methods for implementing prominent quantum algorithms such as the quantum Fourier transform or the Quantum Approximate Optimization Algorithm across a wide range of quantum hardware, including linear, square-grid, hexagonal, ladder and all-to-all connected devices. We show that even moderate increments in connectivity can yield significant efficiency improvements and reach the proven optimum for specific cases. Furthermore, we demonstrate a practical performance advantage of this approach for a wide range of compilation problems and quantum hardware.

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arXiv2025

Fault-tolerant multi-qubit gates in Parity Codes

We present a set of efficiently implementable logical multi-qubit gates in concatenated quantum error correction codes using parity qubits. In particular, we show how fault-tolerant high-weight rotation gates of arbitrary angle can be implemented on single physical qubits of a classical stabilizer code, or on localized regions of full quantum error correction codes. Similarly, we show how transversal CNOT gates can implement logical parity-controlled-NOT operations between arbitrarily many logical qubits. Both operation types can be implemented and in many cases parallelized without the use of lattice surgery or the need for complicated routing operations.

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arXiv2025

Constructive plaquette compilation for the parity architecture

Parity compilation is the challenge of laying out the required constraints for the parity mapping in a local way. We present the first constructive compilation algorithm for the parity architecture using plaquettes for arbitrary higher-order optimization problems. This enables adiabatic protocols, where the plaquette layout can natively be implemented, as well as fully parallelized digital circuits. The algorithm builds a rectangular layout of plaquettes, where in each layer of the rectangle at least one constraint is added. The core idea is that each constraint, consisting of any qubits on the boundary of the rectangle and some new qubits, can be decomposed into plaquettes with a deterministic procedure using ancillas. We show how to pick a valid set of constraints and how this decomposition works. We further give ways to optimize the ancilla count and show how to implement optimization problems with additional constraints.

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arXiv2025

Flexible constraint compilation in the parity architecture

We present tools and methods to generalize parity compilation to digital quantum computing devices with arbitrary connectivity graphs and construct circuit implementations for the constraint Hamiltonian of higher-order constrained binary optimization problems. In particular, we show how even non-local constraints can be efficiently implemented without expensive SWAP gates. We show how the presented tools can be used to optimize the total circuit depth and CNOT count of the quantum approximate optimization algorithm in the parity architecture and highlight the advantages of the flexible compilation using various examples. We derive the relation between the developed gate sequences and the traditional approach that uses SWAP gates. The result can be applied to improve the implementation of many other non-local operators.

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arXiv2025

Fault-tolerant quantum computing with the parity code and noise-biased qubits

We present a fault-tolerant universal quantum computing architecture based on a code concatenation of biased-noise qubits and the parity architecture. The parity architecture can be understood as an LDPC code tailored specifically to obtain any desired logical connectivity from nearest-neighbor physical interactions. The code layout can be dynamically adjusted to algorithmic requirements on-the-fly. This allows for implementations with any desired code distance with a universal set of fault-tolerant gates. In addition to the previously explored tool-sets for concatenated cat codes, our approach features parallelizable interactions between arbitrary sets of qubits by directly addressing the parity qubits in the code. The proposed scheme enables codes with less physical qubit overhead compared to the repetition code with the same code distances, while requiring only weight-3 and weight-4 stabilizers and nearest-neighbor 2D square-lattice connectivity.

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arXiv2025

Optimal Decoder for the Error Correcting Parity Code

We present a two-step decoder for the parity code and evaluate its performance in code-capacity and faulty-measurement settings. For noiseless measurements, we find that the decoding problem can be reduced to a series of repetition codes while yielding near-optimal decoding for intermediate code sizes and achieving optimality in the limit of large codes. In the regime of unreliable measurements, the decoder demonstrates fault-tolerant thresholds above 5% at the cost of decoding a series of independent repetition codes in (1 + 1) dimensions. Such high thresholds, in conjunction with a practical decoder, efficient long-range logical gates, and suitability for planar implementation, position the parity architecture as a promising candidate for demonstrating quantum advantage on qubit platforms with strong noise bias.

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arXiv2025

Minimally Universal Parity Quantum Computing

In parity quantum computing, multi-qubit logical gates are implemented by single-qubit rotations on a suitably encoded state involving auxiliary qubits. Consequently, there is a correspondence between qubit count and the size of the native gate set. One might then wonder: what is the smallest number of auxiliary qubits that still allows for universal parity computing? Here, we demonstrate that the answer is one, if the number of logical qubits is even, and two otherwise. Furthermore, we present a sufficient condition for a given parity gate set to be universal. This leads to a variety of different universal parity gate sets corresponding to different numbers of auxiliary qubits, and more generally contributes to the understanding of which entangling gates are required to augment the set of single-qubit unitaries to perform universal quantum computing. As a consequence, we obtain (i) minimal implementations of the parity framework on e.g., a triangular lattice, (ii) hardware specific implementations of the parity flow framework on e.g., a heavy-hex lattice, and (iii) novel universal resources for measurement-based quantum computation (MBQC).

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arXiv2025

Performance of Parity QAOA for the Signed Max-Cut Problem

The practical implementation of quantum optimization algorithms on noisy intermediate-scale quantum devices requires accounting for their limited connectivity. As such, the Parity architecture was introduced to overcome this limitation by encoding binary optimization problems onto planar quantum chips. We investigate the performance of the Quantum Approximate Optimization Algorithm on the Parity architecture (Parity QAOA) for solving instances of the signed Max-Cut problem on complete and regular graphs. By comparing the algorithms at fixed circuit depth, we demonstrate that Parity QAOA outperforms conventional QAOA implementations based on SWAP networks. Our analysis utilizes Clifford circuits to estimate lower performance bounds for Parity QAOA for problem sizes that would be otherwise inaccessible on classical computers. For single layer circuits we additionally benchmark the recursive variant of the two algorithms, showing that their performance is equal.

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arXiv2025

Multi-Qubit Parity Gates for Rydberg Atoms in Various Configurations

We present a native approach for realizing multi-qubit parity phase gates in neutral atom systems through global phase modulation of a Rydberg excitation laser. By shaping the temporal profile of the laser's phase, we enable high fidelity, time efficient entangling operations between multiple qubits without requiring individual qubit addressing. To mitigate intrinsic noise sources including spontaneous decay and motional effects, we develop a noise-aware optimal control framework that reduces gate errors under the presence of noise while maintaining smooth pulse profiles suitable for experimental implementation. In addition to equidistant qubit arrangements, we explore the impact of non-equidistant atomic configurations, where interaction inhomogeneity becomes significant. In these cases, the flexibility of our control approach helps to compensate for such variations, supporting reliable gate performance across different spatial layouts. These results facilitate the practical implementation of complex, multi-qubit quantum operations in near-term neutral atom quantum processors.

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arXiv2025

Improving success probability in the LHZ parity embedding by computing with quantum walks

The LHZ parity embedding is one of the front-running methods for implementing difficult-to-engineer long-range interactions in quantum optimisation problems. Continuous-time quantum walks are a leading approach for solving quantum optimisation problems. Due to them populating excited states, quantum walks can avoid the exponential gap closing problems seen in other continuous-time techniques such as quantum annealing and adiabatic quantum computation (AQC). An important question therefore, is how continuous-time quantum walks perform in combination with the LHZ parity embedding. By numerically simulating continuous-time quantum walks on 4, 5 and 6 logical qubit Sherrington-Kirkpatrick (SK) Ising spin glass instances embedded onto the LHZ parity architecture, we are able to verify the continued efficacy of heuristics used to estimate the optimal hopping rate and the numerical agreement with the theory behind the location of the lower bound of the LHZ parity constraint strength. In addition, by comparing several different LHZ-based decoding methods, we were able to identify post-readout error correction techniques which were able to improve the success probability of the quantum walk.

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arXiv2024

Runtime Reduction in Linear Quantum Charge-Coupled Devices using the Parity Flow Formalism

Using the Parity Flow formalism, we show that physical SWAP gates can be eliminated in linear hardware architectures, without increasing the total number of two-qubit operations. This has a significant impact on the execution time of quantum circuits in linear Quantum Charge-Coupled Devices (QCCDs), where SWAP gates are implemented by physically changing the position of the ions. Because SWAP gates are one of the most time-consuming operations in QCCDs, our scheme considerably reduces the runtime of the quantum Fourier transform and the quantum approximate optimization algorithm on all-to-all spin models, compared to circuits generated with standard compilers (TKET and Qiskit). While increasing the problem size (and therefore the number of qubits) typically demands longer runtimes, which are constrained by coherence time, our runtime reduction enables a significant increase in the number of qubits at a given coherence time.

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arXiv2024

Scalable Parity Architecture With a Shuttling-Based Spin Qubit Processor

Motivated by the prospect of a two-dimensional square-lattice geometry for semiconductor spin qubits, we explore the realization of the Parity Architecture with quantum dots (QDs). We present sequences of spin shuttling and quantum gates that implement the Parity Quantum Approximate Optimization Algorithm (QAOA) on a lattice constructed of identical unit cells, such that the circuit depth is always constant. We further develop a detailed error model for a hardware-specific analysis of the Parity Architecture and we estimate the errors during one round of Parity QAOA. The model includes a general description of the shuttling errors as a function of the probability distribution function of the valley splitting, which is the main limitation for the performance. We compare our approach to a superconducting transmon qubit chip and we find that with high-fidelity spin shuttling the performance of the spin qubits is competitive or even exceeds the results of the transmons. Finally, we discuss the possibility of decoding the logical quantum state and of quantum error mitigation. We find that already with near-term spin qubit devices a sufficiently low physical error probability can be expected to reliably perform Parity QAOA with a short depth in a regime where the success probability compares favorably to standard QAOA.

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arXiv2024

Low-depth Circuit Implementation of Parity Constraints for Quantum Optimization

We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped constraints in QAOA when using the parity mapping. The circuits can be implemented on any quantum device with nearest-neighbor connectivity on a square-lattice, using only one gate type and one orientation of two-qubit gates at a time. We find an upper bound for the circuit depth which is independent of the system size. The procedure is readily adjustable to hardware-specific restrictions, such as a minimum required spatial distance between simultaneously executed gates, or gates only being simultaneously executable within a subset of all the qubits, for example a single line.

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arXiv2024

Scalable embedding of parity constraints in quantum annealing hardware

One of the main bottlenecks in solving combinatorial optimization problems with quantum annealers is the qubit connectivity in the hardware. A possible solution for larger connectivty is minor embedding. This techniques makes the geometrical properties of the combinatorial optimization problem, encoded as a Hamiltonian, match the properties of the quantum annealing hardware. The embedding itself is a hard computational problem and therefore heuristic algorithms are required. In this work, we present fixed, modular and scalable embeddings that can be used to embed any combinatorial optimization problem described as an Ising Hamiltonian. These embeddings are the result of an extension of the well-known parity mapping, which has been used in the past to map higher-order Ising Hamiltonians to quadratic Hamiltonians, which are suitable for existing quantum hardware. We show how our new embeddings can be mapped to existing quantum annealers and that the embedded Hamiltonian physical properties match the original Hamiltonian properties.

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arXiv2024

Constant Depth Code Deformations in the Parity Architecture

We present a protocol to encode and decode arbitrary quantum states in the parity architecture with constant circuit depth using measurements, local nearest-neighbor and single-qubit operations only. While this procedure typically requires a quadratic overhead of simultaneous qubit measurements, it allows for a simple and low-depth implementation of logical multi-qubit gates in the parity encoding via code deformation. We discuss how such encoding and decoding schemes can be used to flexibly change the size and shape of the underlying code to enable a more efficient implementation of quantum gates or algorithms. We apply the new findings to the QAOA which leads to a constant depth implementation using local gates at the same optimization performance as the standard, potentially non-local, QAOA approach without the parity encoding. Furthermore, we show that our method can reduce the depth of implementing the quantum Fourier transform by a factor of two when allowing measurements.

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arXiv2023

Comparing planar quantum computing platforms at the quantum speed limit

An important aspect that strongly impacts the experimental feasibility of quantum circuits is the ratio of gate times and typical error time scales. Algorithms with circuit depths that significantly exceed the error time scales will result in faulty quantum states and error correction is inevitable. We present a comparison of the theoretical minimal gate time, i.e., the quantum speed limit (QSL), for realistic two- and multi-qubit gate implementations in neutral atoms and superconducting qubits. Subsequent to finding the QSLs for individual gates by means of optimal control theory we use them to quantify the circuit QSL of the quantum Fourier transform and the quantum approximate optimization algorithm. In particular, we analyze these quantum algorithms in terms of circuit run times and gate counts both in the standard gate model and the parity mapping. We find that neutral atom and superconducting qubit platforms show comparable weighted circuit QSLs with respect to the system size.

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arXiv2023

Parity Quantum Optimization: Compiler

We introduce parity quantum optimization with the aim of solving optimization problems consisting of arbitrary $k$-body interactions and side conditions using planar quantum chip architectures. The method introduces a decomposition of the problem graph with arbitrary $k$-body terms using generalized closed cycles of a hypergraph. Side conditions of the optimization problem in form of hard constraints can be included as open cycles containing the terms involved in the side conditions. The generalized parity mapping thus circumvents the need to translate optimization problems to a quadratic unconstrained binary optimization problem (QUBO) and allows for the direct encoding of higher-order constrained binary optimization problems (HCBO) on a square lattice and full parallelizability of gates.

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arXiv2023

Parity Quantum Optimization: Encoding Constraints

Constraints make hard optimization problems even harder to solve on quantum devices because they are implemented with large energy penalties and additional qubit overhead. The parity mapping, which has been introduced as an alternative to the spin encoding, translates the problem to a representation using only parity variables that encodes products of spin variables. In combining exchange interaction and single spin flip terms in the parity representation, constraints on sums and products of arbitrary k-body terms can be implemented without additional overhead in two-dimensional quantum systems.

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