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Xiangwei Jiang

Publications and source records attributed to Xiangwei Jiang.

8 recordsLinked to original sources

ToLL: Topological Layout Learning with Asymmetric Cross-View Structural Distillation for 3D Scene Graph Generation Pretraining

3D Scene Graph (3DSG) generation plays a pivotal role in spatial understanding and affordance perception. To mitigate generalization issues from data scarcity, joint-embedding and generative proxy tasks are proposed to pre-train 3DSG representations on predicate label-free datasets. Currently, generative pre-training usually bypasses the semantic corruption caused by the geometric augmentations in joint-embedding, but cannot avoid a negative problem ``Geometric Shortcut." In this problem, exposing dense object spatial and scale priors will induce models to trivially reconstruct scenes by interpolating object positions, rather than learning the underlying topological constraints provided by edges. To address this issue, we propose a Topological Layout Learning (ToLL) for 3DSG generation pretraining framework. In detail, we design an Anchor-Conditioned Topological Geometry Reasoning. It adopts a recurrent GNN to recover the global layout of zero-centered subgraphs (the non-visible spatial features) by one anchor with sparse spatial prior. Considering the absence of spatial layout information within the objects, it creates an information bottleneck, compelling our model to recover the full scene layout by leveraging predicate representation learning. Moreover, we construct a Structural Multi-view Augmentation to avoid semantic corruption, enhancing 3DSG representations via self-distillation. The extensive experiments on special dataset demonstrate that our ToLL could often improve 3DSG pertaining quality, outperforming state-of-the-art baselines.

cs.CV

Revisiting Document Image Dewarping by Grid Regularization

This paper addresses the problem of document image dewarping, which aims at eliminating the geometric distortion in document images for document digitization. Instead of designing a better neural network to approximate the optical flow fields between the inputs and outputs, we pursue the best readability by taking the text lines and the document boundaries into account from a constrained optimization perspective. Specifically, our proposed method first learns the boundary points and the pixels in the text lines and then follows the most simple observation that the boundaries and text lines in both horizontal and vertical directions should be kept after dewarping to introduce a novel grid regularization scheme. To obtain the final forward mapping for dewarping, we solve an optimization problem with our proposed grid regularization. The experiments comprehensively demonstrate that our proposed approach outperforms the prior arts by large margins in terms of readability (with the metrics of Character Errors Rate and the Edit Distance) while maintaining the best image quality on the publicly-available DocUNet benchmark.

eess.IV

Understanding Hot Carrier Reliability in FinFET Technology from Trap-based Approach

In this paper, the recent advances of our studies on hot carrier degradation (HCD) are presented from trap-based approach. The microscopic speculation of interface trap generation is carried out by time-dependent DFT (TDDFT) simulation in "real-time". Two types of oxide traps contributing to HCD are identified from experiments. Combining the contributions of interface and oxide traps, a unified compact model has been proposed which can accurately predict hot carrier degradation and variation in full Vgs/Vds bias. The trap locations, degradation contributions and temperature dependence are studied in detail. In addition, the mixed mode reliability of HCD-BTI coupling through self-heating and under off-state stress are discussed.

cond-mat.mes-hall

Anharmonic corrections to the multiphonon deep-level charge capture ab initio calculations for semiconductors

Nonradiative carrier recombination at semiconductor deep centers is of great importance to both fundamental physics and device engineering. In this letter, we provide a revised analysis of K. Huang's original nonradiative multi-phonon (NMP) theory with ab initio calculations. First, we identify at first-principle level that Huang's concise formula gives the same results as the matrix based formula, and Huang's high temperature formula provides an analytical expression for the coupling constant in Marcus theory. Secondly, the anharmonic effects are corrected by taking into account local phonon mode variation at different charge states of the defect. The corrected capture rates for defects in GaN and SiC agree well with experiments.

cond-mat.mtrl-sci

High-Performance Logic and Memory Devices Based on a Dual-Gated MoS2 Architecture

In this work, we demonstrate a dual-gated (DG) MoS2 field effect transistors (FETs) in which the degraded switching performance of multilayer MoS2 can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (~100 mV/dec for 5 nm thickness), and high on/off current ratio (greater than 107 for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (VTH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS2-FETs, and a DRAM unit cell with a long retention time of 1260 ms are realized. A large-scale isolated MoS2 DG-FETs based on CVD-synthesized continuous films is also demonstrated, which shows potential applications for future wafer-scale digital and low-power electronics.

physics.app-ph

MoS$_2$ Dual-gate Transistors with Electrostatically Doped Contacts

Two-dimensional (2D) transition metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS2) have been intensively investigated because of their exclusive physical properties for advanced electronics and optoelectronics. In the present work, we study the MoS2 transistor based on a novel tri-gate device architecture, with dual-gate (Dual-G) in the channel and the buried side-gate (Side-G) for the source/drain regions. All gates can be independently controlled without interference. For a MoS2 sheet with a thickness of 3.6 nm, the Schottky barrier (SB) and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G. Thus, the extrinsic resistance can be effectively lowered, and a boost of the ON-state current can be achieved. Meanwhile, the channel control remains efficient under the Dual-G mode, with an ON-OFF current ratio of 3E7 and subthreshold swing of 83 mV/decade. The corresponding band diagram is also discussed to illustrate the device operation mechanism. This novel device structure opens up a new way toward fabrication of high-performance devices based on 2D-TMDs.

physics.app-ph

A large-scale first-principles quantum transport simulation method using plane waves

As the characteristic lengths of advanced electronic devices are approaching the atomic scale, ab initio simulation method, with fully consideration of quantum mechanical effects, becomes essential to study the quantum transport phenomenon in them. However, current widely used non-equilibrium Green's function (NEGF) approach is based on atomic basis set, which usually can only study small system with less than 1000 atoms in practice. Here we present a large-scale quantum transport simulation method using plane waves basis, based on the previously developed plane wave approach (Phys. Rev. B 72, 045417). By applying several high-efficiency parallel algorithms, such as linear-scale ground-state density function theory (DFT) algorithm, folded spectrum method, and filtering technique, we demonstrate that our new method can simulate the system with several thousands of atoms. We also use this method to study several nanowires with about 4000 copper atoms, and show how the shape and point defect affect the transport properties of them. Such quantum simulation method will be useful to investigate and design nanoscale devices, especially the on-die interconnects.

cond-mat.mes-hall

Gate-controlled reversible rectifying behaviour in tunnel contacted atomically-thin MoS$_{2}$ transistor

Atomically-thin 2D semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their full acceptance as compliant materials for integration in logic devices. Two key-components to master are the barriers at metal/semiconductor interfaces and the mobility of the semiconducting channel, which endow the building-blocks of ${pn}$ diode and field effect transistor. Here, we have devised a reverted stacking technique to intercalate a wrinkle-free h-BN tunnel layer between MoS$_{2}$ channel and contacting electrodes. Vertical tunnelling of electrons therefore makes it possible to suppress the Schottky barriers and Fermi level pinning, leading to homogeneous gate-control of the channel chemical potential across the bandgap edges. The observed unprecedented features of ambipolar ${pn}$ to ${np}$ diode, which can be reversibly gate tuned, paves the way for future logic applications and high performance switches based on atomically thin semiconducting channel.

physics.app-ph