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Z. Dong

Publications and source records attributed to Z. Dong.

8 recordsLinked to original sources

CroBIM-V: Memory-Quality Controlled Remote Sensing Referring Video Object Segmentation

Remote sensing video referring object segmentation (RS-RVOS) is challenged by weak target saliency and severe visual information truncation in dynamic scenes, making it extremely difficult to maintain discriminative target representations during segmentation. Moreover, progress in this field is hindered by the absence of large-scale dedicated benchmarks, while existing models are often affected by biased initial memory construction that impairs accurate instance localization in complex scenarios, as well as indiscriminate memory accumulation that encodes noise from occlusions or misclassifications, leading to persistent error propagation. This paper advances RS-RVOS research through dual contributions in data and methodology. First, we construct RS-RVOS Bench, the first large-scale benchmark comprising 111 video sequences, about 25,000 frames, and 213,000 temporal referring annotations. Unlike common RVOS benchmarks where many expressions are written with access to the full video context, our dataset adopts a strict causality-aware annotation strategy in which linguistic references are generated solely from the target state in the initial frame. Second, we propose a memory-quality-aware online referring segmentation framework, termed Memory Quality Control with Segment Anything Model (MQC-SAM). MQC-SAM introduces a temporal motion consistency module for initial memory calibration, leveraging short-term motion trajectory priors to correct structural deviations and establish accurate memory anchoring. Furthermore, it incorporates a decoupled attention-based memory integration mechanism with dynamic quality assessment, selectively updating high-confidence semantic features while filtering unreliable information, thereby effectively preventing error accumulation and propagation. Extensive experiments on RS-RVOS Bench demonstrate that MQC-SAM achieves state-of-the-art performance.

cs.CV

Multiple-Step Quantized Triplet STDP Implemented with Memristive Synapse

As an extension of the pairwise spike-timing-dependent plasticity (STDP) learning rule, the triplet STDP is provided with greater capability in characterizing the synaptic changes in the biological neural cell. In this work, a novel mixed-signal circuit scheme, called multiple-step quantized triplet STDP, is designed to provide a precise and flexible implementation of coactivation triplet STDP learning rule in memristive synapse spiking neural network. The robustness of the circuit is greatly improved through the utilization of pulse-width encoded weight modulation signals. The circuit performance is studied through the simulations which are carried out in MATLAB Simulink & Simscape, and assessment is given by comparing the results of circuits with the algorithmic approaches.

eess.SY

Implementation of Multiple-Step Quantized STDP Based on Novel Memristive Synapses

Memristors have been widely studied as artificial synapses in neuromorphic circuits, due to their functional similarity with biological synapses, low operating power, and high integration density. In this work, a memristive synapse, composed of four memristors and two resistors, for SNN is designed and utilized for a neuron circuit implementing the robust spike-timing dependent plasticity learning. The synapse can be either excitatory or inhibitory by rationally arranging the resistors in the circuit. This is the first of its kind, enabling Hebbian and anti-Hebbian training without requiring additional processing of neural signals. Then, a neuron circuit is designed based on the proposed synapses. The robustness and compatibility of this neuron circuit are greatly enhanced by employing the clock-based square-wave pulsed to transmit spikes and modulate the synaptic weight. To study the performance of proposed synapses and circuit, simulations based on behavior models are carried out in the MATLAB Simulink and Simscape. Specially, a memristor model with balanced flexibility, efficiency, convergence, and emulation performance, is developed through including the nonlinear Joule effect. Using this memristor model in pattern learning, the influence of weak signal-induced weight variation on circuit performance can be rigorously assessed. This proposed circuit could give some inspiration for combining the analog memristive synapse and leaky integrate-and-fire neuron with digital control units, prompting their development as edge computing devices.

cs.ET

Fizeau Drag in Graphene Plasmonics

Dragging of light by moving dielectrics was predicted by Fresnel and verified by Fizeau's celebrated experiments with flowing water. This momentous discovery is among the experimental cornerstones of Einstein's special relativity and is well understood in the context of relativistic kinematics. In contrast, experiments on dragging photons by an electron flow in solids are riddled with inconsistencies and so far eluded agreement with the theory. Here we report on the electron flow dragging surface plasmon polaritons (SPPs): hybrid quasiparticles of infrared photons and electrons in graphene. The drag is visualized directly through infrared nano-imaging of propagating plasmonic waves in the presence of a high-density current. The polaritons in graphene shorten their wavelength when launched against the drifting carriers. Unlike the Fizeau effect for light, the SPP drag by electrical currents defies the simple kinematics interpretation and is linked to the nonlinear electrodynamics of the Dirac electrons in graphene. The observed plasmonic Fizeau drag enables breaking of time-reversal symmetry and reciprocity at infrared frequencies without resorting to magnetic fields or chiral optical pumping.

cond-mat.mes-hall

Hardware and software status of QCDOC

QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

hep-lat

Status of and performance estimates for QCDOC

QCDOC is a supercomputer designed for high scalability at a low cost per node. We discuss the status of the project and provide performance estimates for large machines obtained from cycle accurate simulation of the QCDOC ASIC.

hep-lat

Status of the QCDOC project

A status report is given of the QCDOC project, a massively parallel computer optimized for lattice QCD using system-on-a-chip technology. We describe several of the hardware and software features unique to the QCDOC architecture and present performance figures obtained from simulating the current VHDL design of the QCDOC chip with single-cycle accuracy.

hep-lat

QCDOC: A 10-teraflops scale computer for lattice QCD

The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from ``QCD On a Chip''.

hep-lat