Zexuan Zhao | Searcharxiv

arXiv2026

Behavioral-Level Simulation of Digital Readout for COFFEE at LHCb Upstream Pixel Tracker

COFFEE series is a HVCMOS pixel sensor using the advanced 55 nm process, currently being developed for the Upstream Pixel (UP) tracker of the LHCb Upgrade II. To ensure that COFFEE will be able to handle the particle hit rates at UP tracker, which reach a maximum of 322.5 MHz/chip, detailed simulation of the digital readout circuitry was performed. Simulation results show that the column-drain readout mechanism achieves nearly 100\% efficiency when the single readout cycle does not exceed 100 ns. Meanwhile, the buffer depth and memory resources required for the peripheral readout adapted to the BXID-sharing data format are also evaluated. These provide guidance for the design of COFFEE. The column-drain readout mechanism was used in COFFEE3 (fabricated in 2025), while the peripheral readout architecture adapted to the BXID-sharing data format is implemented in CHiR (taped out in early 2026).

physics.ins-det↗

arXiv2026

Design and First Results of COFFEE3: A 55nm HVCMOS Pixel Sensor Prototype for High-Energy Physics Applications

Motivated by the stringent requirements of the Upstream Pixel (UP) tracker in the LHCb Upgrade II and the Inner Tracking detector (ITK) of the Circular Electron Positron Collider, the COFFEE series of pixel sensor chips have been developed using a 55nm High-Voltage CMOS (HVCMOS) process. The primary objective is to achieve a time resolution of a few nanoseconds under a hit density of up to 100 MHz/cm$^2$, while maintaining fine spatial resolution ($\sim$10 $\mu$m) and reasonable power consumption ($<$200 mW/cm$^2$). Building on the process validation of the COFFEE2 prototype, this work presents the design and preliminary test results of COFFEE3-a prototype integrating two distinct readout architectures. Architecture 1, tailored for the current triple-well process, adopts NMOS-only in-pixel circuitry and innovative column-level readout to handle high hit densities. The time walk of pixel-level signal is controlled within 10 ns, and the Time of Arrival (TOA) and Time over Threshold (TOT) are measured with a system clock with the period of 25 ns in peripheral circuits. Architecture 2, developed for future possible processes with p-type buried layer isolation, features pixel-level time measurement and storage. A chip-level Time-to-Digital Converter (TDC) is used and the part of Voltage-Controlled Delay Line (VCDL) is copied in each pixel to get a high time resolution. The TOA resolution is estimated to be 4.2 ns and the TOT resolution 8.4 ns. COFFEE3, with a layout size of 3$\times$4 mm$^2$, was manufactured and has undergone preliminary tests. Charge injection tests for analog circuits, and laser tests for full readout chains, confirm that both architectures operate as expected. Next step work will focus on characterizing key performance such as the timing resolution, radiation hardness, and tracking performance of minimum ionising particles.

physics.ins-det↗

arXiv2020

"Drunk Man" Saves Our Lives: Route Planning by a Biased Random Walk Mode

Based on the hurricane striking Puerto Rico in 2017, we developed a transportable disaster response system "DroneGo" featuring a drone fleet capable of delivering the medical package and videoing roads. Covering with a genetic algorithm and a biased random walk model mimicking a drunk man to explore feasible routes on a field with altitude and road information. A proposal mechanism guaranteeing stochasticity and an objective function biasing randomness are combined. The results showed high performance though time-consuming.

cs.RO↗