arXiv subjects

Zsolt Tőkei

Publications and source records attributed to Zsolt Tőkei.

7 recordsLinked to original sources

arXiv2025

Characterization of NbTiN/HZO/NbTiN MIM Capacitors for high frequency AC Clock & Power Distribution Network for Superconducting Digital Circuits

A resonant clock-power distribution network is critical for scaling energy efficient superconducting digital technology to practical high integration density circuits. High-k, tunable capacitors enable implementation of a resonant power delivery network supporting circuits with up to 400 Mdevices/cm2. We report the cryogenic characterization of Metal-Insulator-Metal capacitors using a Hafnium Zirconium Oxide (HZO) ferroelectric insulating layer and Niobium Titanium Nitride (NbTiN) superconducting electrodes. The fabricated chip includes capacitor arrays for low frequency characterization and a half-wave transmission line resonator for RF characterization. A specific capacitance of 3 uF/cm2, DC leakage current of 10-8 A/cm2 at 2 V and a constant 5 percent tunability up to 4 GHz were measured at 2.6 K.

cond-mat.supr-con↗

arXiv2024

Selecting Alternative Metals for Advanced Interconnects

Interconnect resistance and reliability have emerged as critical factors limiting the performance of advanced CMOS circuits. With the slowdown of transistor scaling, interconnect scaling has become the primary driver of continued circuit miniaturization. The associated scaling challenges for interconnects are expected to further intensify in future CMOS technology nodes. As interconnect dimensions approach the 10 nm scale, the limitations of conventional Cu dual-damascene metallization are becoming increasingly difficult to overcome, spurring over a decade of focused research into alternative metallization schemes. The selection of alternative metals is a highly complex process, requiring consideration of multiple criteria, including resistivity at reduced dimensions, reliability, thermal performance, process technology readiness, and sustainability. This tutorial introduces the fundamental criteria for benchmarking and selecting alternative metals and reviews the current state of the art in this field. It covers materials nearing adoption in high-volume manufacturing, materials currently under active research, and potential future directions for fundamental study. While early alternatives to Cu metallization have recently been introduced in commercial CMOS devices, the search for the optimal interconnect metal remains ongoing.

physics.app-ph↗

arXiv2024

Cu$_x$Al$_{1-x}$ films as Alternatives to Copper for Advanced Interconnect Metallization

Cu$_x$Al$_{1-x}$ thin films with $0.2 \le x \le 0.7$ have been studied as potential alternatives for the metallization of advanced interconnects. First-principles simulations were used to obtain the Cu$_x$Al$_{1-x}$ electronic structure and cohesive energy to benchmark different intermetallics and their prospects for interconnect metallization. Next, thin Cu$_x$Al$_{1-x}$ films were deposited by PVD with thicknesses in the range between 3 and 28 nm. The lowest resistivities of 9.5 $μΩ$cm were obtained for 28 nm thick stochiometric CuAl and CuAl$_2$ after 400$^\circ$C post-deposition annealing. Based on the experimental results, we discuss the main challenges for the studied aluminides from an interconnect point of view, namely the control of the film stoichiometry, the phase separation observed for off-stoichiometric CuAl and CuAl$_2$, as well as the presence of a nonstoichiometric surface oxide.

cond-mat.mtrl-sci↗

arXiv2024

Al$_3$Sc thin films for advanced interconnect applications

Al$_x$Sc$_{1-x}$ thin films have been studied with compositions around Al$_3$Sc ($x$ = 0.75) for potential interconnect metallization applications. As-deposited 25 nm thick films were x-ray amorphous but crystallized at 190°C, followed by recrystallization at 440°C. After annealing at 500°C, 24 nm thick stoichiometric Al$_3$Sc showed a resistivity of 12.6 $μΩ$cm, limited by a combination of grain boundary and point defect (disorder) scattering. Together with ab initio calculations that found a mean free path of the charge carriers of 7 nm for stoichiometric Al$_3$Sc, these results indicate that Al$_3$Sc bears promise for future interconnect metallization schemes. Challenges remain in minimizing the formation of secondary phases as well as in the control of the non-stoichiometric surface oxidation and interfacial reactions with underlying dielectrics.

cond-mat.mtrl-sci↗

arXiv2023

Properties of Nb\_xTi\_{(1-x)}N thin films deposited on 300 mm silicon wafers for upscaling superconducting digital circuits

Scaling superconducting digital circuits requires fundamental changes in the current material set and fabrication process. The transition to 300 mm wafers and the implementation of advanced lithography are instrumental in facilitating mature CMOS processes, ensuring uniformity, and optimizing the yield. This study explores the properties of NbxTi(1-x)N films fabricated by magnetron DC sputtering on 300 mm Si wafers. As a promising alternative to traditional Nb in device manufacturing, NbxTi(1-x)N offers numerous advantages, including enhanced stability and scalability to smaller dimensions, in both processing and design. As a ternary material, NbxTi(1-x)N allows engineering material parameters by changing deposition conditions. The engineered properties can be used to modulate device parameters through the stack and mitigate failure modes. We report characterization of NbxTi(1-x)N films at less than 2% thickness variability, 2.4% Tc variability and 3% composition variability. The films material properties such as resistivity (140-375 Ωcm) and critical temperature Tc (4.6 K - 14.1 K) are correlated with stoichiometry and morphology of the films. Our results highlight the significant influence of deposition conditions on crystallographic texture along the films and its correlation with Tc.

cond-mat.supr-con↗

arXiv2021

Ab initio screening of metallic MAX ceramics for advanced interconnect applications

The potential of a wide range of layered ternary carbide and nitride MAX phases as conductors in interconnect metal lines in advanced CMOS technology nodes has been evaluated using automated first principles simulations based on density functional theory. The resistivity scaling potential of these compounds, i.e. the sensitivity of their resistivity to reduced line dimensions, has been benchmarked against Cu and Ru by evaluating their transport properties within a semiclassical transport formalism. In addition, their cohesive energy has been assessed as a proxy for the resistance against electromigration and the need for diffusion barriers. The results indicate that numerous MAX phases show promise as conductors in interconnects of advanced CMOS technology nodes.

cond-mat.mtrl-sci↗

arXiv2015

Resistivity scaling and electron relaxation times in metallic nanowires

We study the resistivity scaling in nanometer-sized metallic wires due to surface roughness and grain-boundaries, currently the main cause of electron scattering in nanoscaled interconnects. The resistivity has been obtained with the Boltzmann transport equation, adopting the relaxation time approximation (RTA) of the distribution function and the effective mass approximation for the conducting electrons. The relaxation times are calculated exactly, using Fermi's golden rule, resulting in a correct relaxation time for every sub-band state contributing to the transport. In general, the relaxation time strongly depends on the sub-band state, something that remained unclear with the methods of previous work. The resistivity scaling is obtained for different roughness and grain-boundary properties, showing large differences in scaling behavior and relaxation times. Our model clearly indicates that the resistivity is dominated by grain-boundary scattering, easily surpassing the surface roughness contribution by a factor of 10.

cond-mat.mes-hall↗