Gate Bias Stress in Pentacene Field-Effect-Transistors: Charge Trapping in the Dielectric or Semiconductor

Roger Häusermann; Bertram Batlogg

doi:10.1063/1.3628297

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arXiv · 1106.4636

Gate Bias Stress in Pentacene Field-Effect-Transistors: Charge Trapping in the Dielectric or Semiconductor

Roger Häusermann·Bertram Batlogg

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Abstract

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO$_2$ and Cytop). We show, it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone, or in the dielectric.

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Roger Häusermann, Bertram Batlogg. 2011-08-04. Gate Bias Stress in Pentacene Field-Effect-Transistors: Charge Trapping in the Dielectric or Semiconductor. https://doi.org/10.1063/1.3628297

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