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arXiv · 1203.4811

Few Electron Limit of n-type Metal Oxide Semiconductor Single Electron Transistors

Enrico Prati·Marco De Michielis·Matteo Belli·Simone Cocco·Marco Fanciulli·Dharmraj Kotekar-Patil·Matthias Ruoff·Dieter P. Kern·David A. Wharam·Arjan Verduijn·Giuseppe Tettamanzi·Sven Rogge·Benoit Roche·Romain Wacquez·Xavier Jehl·Maud Vinet·Marc Sanquer
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Abstract

We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a Current Spin Density Functional Theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronics and quantum variables based devices.

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Enrico Prati, Marco De Michielis, Matteo Belli, Simone Cocco, Marco Fanciulli, Dharmraj Kotekar-Patil, Matthias Ruoff, Dieter P. Kern, David A. Wharam, Arjan Verduijn, Giuseppe Tettamanzi, Sven Rogge, Benoit Roche, Romain Wacquez, Xavier Jehl, Maud Vinet, Marc Sanquer. 2012-03-21. Few Electron Limit of n-type Metal Oxide Semiconductor Single Electron Transistors. https://doi.org/10.1088/0957-4484/23/21/215204

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