A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime - Part II Extrinsic Elements, Performance Assessment, and Design Optimization

Chi-Shuen Lee; Eric Pop; Aaron D. Franklin; Wilfried Haensch; H. -S. Philip Wong

doi:10.1109/ted.2015.2457424

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arXiv · 1503.04398

A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime - Part II Extrinsic Elements, Performance Assessment, and Design Optimization

Chi-Shuen Lee·Eric Pop·Aaron D. Franklin·Wilfried Haensch·H. -S. Philip Wong

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Abstract

We present a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) including contact resistance, direct source-to-drain and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects and is used to study the trade-offs between the drive current and leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/{\mu}m will enable CNFET technology to meet the ITRS target of drive current (1.33 mA/{\mu}m), which is within reach of modern experimental capabilities

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Chi-Shuen Lee, Eric Pop, Aaron D. Franklin, Wilfried Haensch, H. -S. Philip Wong. 2015-03-15. A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime - Part II Extrinsic Elements, Performance Assessment, and Design Optimization. https://doi.org/10.1109/ted.2015.2457424

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