arXiv subjects

H. -S. Philip Wong

Publications and source records attributed to H. -S. Philip Wong.

At least 19 recordsLinked to original sources

arXiv2026

Cross-Domain Acceleration of Open Modification Search: From Commodity Platforms to Emerging Memory and Storage Devices

Open modification search (OMS) in mass spectrometry (MS) is a data-intensive workload whose performance is dominantly limited by reference data movement rather than computation. Prior OMS accelerators have largely been evaluated in isolation, making it difficult to understand system-level trade-offs across platforms. This paper presents the first workload-driven, cross-platform survey of accelerators for MS search by studying not only commodity platforms, but also emerging memory- and storage-centric architectures, including GPUs, near-storage FPGAs, DRAM near-memory processing, ReRAM/PCM in-memory processing, and 3D NAND/FeNAND in-storage processing, under consistent algorithmic and accuracy assumptions. Leveraging a binary hyperdimensional computing (HDC)-based OMS formulation that reduces similarity evaluation to lightweight bitwise primitives and tolerates device-level non-idealities, we enable a robust execution on memory-centric architectures despite device-level non-idealities and limited computing capability. Overall, this study identifies memory- and storage-centric architectures as a key architectural breakthrough for large-scale, high-speed search acceleration, delivering up to >100x speedup and >40,000x improvement in energy efficiency.

cs.AR↗

arXiv2026

Contacts to Low-Dimensional Semiconductors: Physical Theory and Analytical Model

Metal contacts to low-dimensional semiconductors are critical for nanoelectronics, yet a general physical description has remained elusive. We present an analytical model for metal-induced gap states (MIGS), revealing a universal scaling law governed by semiconductor dimensionality. Linking MIGS to transport observables, we provide a unified formulation of Schottky barrier height, transfer length, and contact resistance. Our model explains recent experiments on carbon nanotubes and 2D materials, clarifying the fundamental criteria for achieving scalable, low-resistance contacts.

cond-mat.mes-hall↗

arXiv2026

Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler

As memory increasingly dominates system cost and energy, heterogeneous on-chip memory systems that combine technologies with complementary characteristics are becoming essential. Gain Cell RAM (GCRAM) offers higher density, lower power, and tunable retention, expanding the design space beyond conventional SRAM. To this end, we create an OpenGCRAM compiler supporting both SRAM and GCRAM. It generates macro-level designs and layouts for commercial CMOS processes and characterizes area, delay, and power across user-defined configurations. The tool enables systematic identification of optimal heterogeneous memory configurations for AI tasks under specified performance metrics.

cs.AR↗

arXiv2025

Channel-last gate-all-around nanosheet oxide semiconductor transistors

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

cond-mat.mtrl-sci↗

arXiv2025

Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.

cond-mat.mtrl-sci↗

arXiv2025

The Future of Memory: Limits and Opportunities

Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large numbers of CPUs. We argue two practical engineering challenges, scaling and signaling, limit such designs. We propose the opposite approach. Rather than create large, shared, homogenous memories, systems explicitly break memory up into smaller slices more tightly coupled with compute elements. Leveraging advances in 2.5D/3D integration, this compute-memory node provisions private local memory, enabling accesses of node-exclusive data through micrometer-scale distances, and dramatically reduced access cost. In-package memory elements support shared state within a processor, providing far better bandwidth and energy-efficiency than DRAM, which is used as main memory for large working sets and cold data. Hardware making memory capacities and distances explicit allows software to efficiently compose this hierarchy, managing data placement and movement.

cs.AR↗

arXiv2025

GainSight: A Unified Framework for Data Lifetime Profiling and Heterogeneous Memory Composition

As AI workloads drive increasing memory requirements, domain-specific accelerators need higher-density on-chip memory beyond what current SRAM scaling trends can provide. Simultaneously, the vast amounts of short-lived data in these workloads make SRAM overprovisioned in retention capability. To address this mismatch, we propose a wholesale shift from uniform SRAM arrays to heterogeneous on-chip memory, incorporating denser short-term RAM (StRAM) devices whose limited retention times align with transient data lifetimes. To facilitate this shift, we introduce GainSight, the first comprehensive, open-source framework that aligns dynamic, fine-grained workload lifetime profiles with memory device characteristics to enable generation of optimal StRAM memory compositions. GainSight combines retargetable profiling backends with an architecture-agnostic analytical frontend. The various backends capture cycle-accurate data lifetimes, while the frontend correlates workload patterns with StRAM retention properties to generate optimal memory compositions and project performance. GainSight elevates data lifetime to a first-class design consideration for next-generation AI accelerators, enabling systematic exploitation of data transience for improved on-chip memory density and efficiency. Applying GainSight to MLPerf Inference and PolyBench workloads reveals that 64.3% of first-level GPU cache accesses and 79.01% of systolic array scratchpad accesses exhibit sub-microsecond lifetimes suitable for high-density StRAM, with optimal heterogeneous on-chip memory compositions achieving up to 3x active energy and 4x area reductions compared to uniform SRAM hierarchies. To facilitate adoption and further research, GainSight is open-sourced at https://gainsight.stanford.edu/.

cs.AR↗

arXiv2025

OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads

Gain Cell memory (GCRAM) offers higher density and lower power than SRAM, making it a promising candidate for on-chip memory in domain-specific accelerators. To support workloads with varying traffic and lifetime metrics, GCRAM also offers high bandwidth, ultra low leakage power and a wide range of retention times, which can be adjusted through transistor design (like threshold voltage and channel material) and on-the-fly by changing the operating voltage. However, designing and optimizing GCRAM sub-systems can be time-consuming. In this paper, we present OpenGCRAM, an open-source GCRAM compiler capable of generating GCRAM bank circuit designs and DRC- and LVS-clean layouts for commercially available foundry CMOS, while also providing area, delay, and power simulations based on user-specified configurations (e.g., word size and number of words). OpenGCRAM enables fast, accurate, customizable, and optimized GCRAM block generation, reduces design time, ensure process compliance, and delivers performance-tailored memory blocks that meet diverse application requirements.

cs.AR↗

arXiv2025

High-field Breakdown and Thermal Characterization of Indium Tin Oxide Transistors

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity and heterogeneous interfaces suggest that their performance may be severely limited by self-heating, especially at higher power and device densities. Here, we investigate the high-field breakdown of ultrathin (~4 nm) amorphous indium tin oxide (ITO) transistors with scanning thermal microscopy (SThM) and multiphysics simulations. The ITO devices break irreversibly at channel temperatures of ~180 °C and ~340 °C on SiO${_2}$ and HfO${_2}$ substrates, respectively, with failure primarily caused by thermally-induced compressive strain near the device contacts. Combining SThM measurements with simulations allows us to estimate a thermal boundary conductance (TBC) of 35 ${\pm}$ 12 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on SiO${_2}$, and 51 ${\pm}$ 14 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on HfO${_2}$. The latter also enables significantly higher breakdown power due to better heat dissipation and closer thermal expansion matching. These findings provide insights into the thermo-mechanical limitations of indium-based amorphous oxide transistors, which are important for more reliable and high-performance logic and memory applications.

physics.app-ph↗

arXiv2024

Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory

Open Modification Search (OMS) is a promising algorithm for mass spectrometry analysis that enables the discovery of modified peptides. However, OMS encounters challenges as it exponentially extends the search scope. Existing OMS accelerators either have limited parallelism or struggle to scale effectively with growing data volumes. In this work, we introduce an OMS accelerator utilizing multi-level-cell (MLC) RRAM memory to enhance storage capacity by 3x. Through in-memory computing, we achieve up to 77x faster data processing with two to three orders of magnitude better energy efficiency. Testing was done on a fabricated MLC RRAM chip. We leverage hyperdimensional computing to tolerate up to 10% memory errors while delivering massive parallelism in hardware.

cs.AR↗

arXiv2023

Neural Network Compression for Noisy Storage Devices

Compression and efficient storage of neural network (NN) parameters is critical for applications that run on resource-constrained devices. Despite the significant progress in NN model compression, there has been considerably less investigation in the actual \textit{physical} storage of NN parameters. Conventionally, model compression and physical storage are decoupled, as digital storage media with error-correcting codes (ECCs) provide robust error-free storage. However, this decoupled approach is inefficient as it ignores the overparameterization present in most NNs and forces the memory device to allocate the same amount of resources to every bit of information regardless of its importance. In this work, we investigate analog memory devices as an alternative to digital media -- one that naturally provides a way to add more protection for significant bits unlike its counterpart, but is noisy and may compromise the stored model's performance if used naively. We develop a variety of robust coding strategies for NN weight storage on analog devices, and propose an approach to jointly optimize model compression and memory resource allocation. We then demonstrate the efficacy of our approach on models trained on MNIST, CIFAR-10 and ImageNet datasets for existing compression techniques. Compared to conventional error-free digital storage, our method reduces the memory footprint by up to one order of magnitude, without significantly compromising the stored model's accuracy.

cs.LG↗

arXiv2022

Improved Gradual Resistive Switching Range and 1000x On/Off Ratio in HfOx RRAM Achieved with a $Ge_2Sb_2Te_5$ Thermal Barrier

Gradual switching between multiple resistance levels is desirable for analog in-memory computing using resistive random-access memory (RRAM). However, the filamentary switching of $HfO_x$-based conventional RRAM often yields only two stable memory states instead of gradual switching between multiple resistance states. Here, we demonstrate that a thermal barrier of $Ge_2Sb_2Te_5$ (GST) between $HfO_x$ and the bottom electrode (TiN) enables wider and weaker filaments, by promoting heat spreading laterally inside the $HfO_x$. Scanning thermal microscopy suggests that $HfO_x+GST$ devices have a wider heating region than control devices with only $HfO_x$, indicating the formation of a wider filament. Such wider filaments can have multiple stable conduction paths, resulting in a memory device with more gradual and linear switching. The thermally-enhanced $HfO_x+GST$ devices also have higher on/off ratio ($>10^3$) than control devices ($<10^2$), and a median set voltage lower by approximately 1 V (~35%), with a corresponding reduction of the switching power. Our $HfO_x+GST$ RRAM shows 2x gradual switching range using fast (~ns) identical pulse trains with amplitude less than 2 V.

physics.app-ph↗

arXiv2022

Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies

Semiconductor innovation drives improvements to technologies that are critical to modern society. The country that successfully accelerates semiconductor innovation is positioned to lead future semiconductor-driven industries and benefit from the resulting economic growth. It is our view that a next generation infrastructure is necessary to accelerate and enhance semiconductor innovation in the U.S. In this paper, we propose such an advanced infrastructure composed of a national network of facilities with enhancements in technology and business models. These enhancements enable application-driven and challenge-based research and development, and ensure that facilities are accessible and sustainable. The main tenets are: a challenge-driven operational model, a next-generation infrastructure to serve that operational model, technology innovations needed for advanced facilities to speed up learning cycles, and innovative cost-effective business models for sustainability. Ultimately, the expected outcomes of such a participatory, scalable, and sustainable nation-level advanced infrastructure will have tremendous impact on government, industry, and academia alike.

cs.OH↗

arXiv2022

Statistical Analysis of Contacts to Synthetic Monolayer MoS2

Two-dimensional (2D) semiconductors are promising candidates for scaled transistors because they are immune to mobility degradation at the monolayer limit. However, sub-10 nm scaling of 2D semiconductors, such as MoS2, is limited by the contact resistance. In this work, we show for the first time a statistical study of Au contacts to chemical vapor deposited monolayer MoS2 using transmission line model (TLM) structures, before and after dielectric encapsulation. We report contact resistance values as low as 330 ohm-um, which is the lowest value reported to date. We further study the effect of Al2O3 encapsulation on variability in contact resistance and other device metrics. Finally, we note some deviations in the TLM model for short-channel devices in the back-gated configuration and discuss possible modifications to improve the model accuracy.

cond-mat.mtrl-sci↗

arXiv2021

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor

We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and timing analysis to evaluate system-level performance of new CMOS technologies. As the impact of parasitic resistances and capacitances continues to increase with dimensional downscaling, component-level optimization alone becomes insufficient, calling for a holistic assessment and optimization methodology across the boundaries between devices, interconnects, circuits, and systems. The physical implementation flow in DISPEL enables realistic analysis of complex wires and vias in VLSI systems and their impact on the chip power, speed, and area, which simple circuit simulations cannot capture. To demonstrate the use of DISPEL, a 32-bit commercial processor core is implemented using theoretical n-type MoS2 and p-type Black Phosphorous (BP) planar FETs at a projected 5-nm node, and the performance is benchmarked against Si FinFETs. While the superior gate control of the MoS2/BP FETs can theoretically provide 51% reduction in the iso-frequency energy consumption, the actual performance can be greatly limited by the source/drain contact resistances. With the large amount of data generated by DISPEL, a neural-network is trained to predict the key performance metrics of the 32-bit processor core using the characteristics of transistors and interconnects as the input features without the need to go through the time-consuming physical implementation flow. The machine learning algorithms show great potentials as a means for evaluation and optimization of new CMOS technologies and identifying the most significant technology design parameters.

cs.ET↗

arXiv2021

Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS$_2$ films at 560 C in 50 min, within the 450-to-600 C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ~140 $\mathrm{μA/μm}$ at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS$_2$ grown below 600 C using solid-source precursors. The effective mobility from transfer length method test structures is $\mathrm{29 \pm 5\ cm^2V^{-1}s^{-1}}$ at $\mathrm{6.1 \times 10^{12}\ cm^{-2}}$ electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

physics.app-ph↗

arXiv2021

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory

Realizing today's cloud-level artificial intelligence functionalities directly on devices distributed at the edge of the internet calls for edge hardware capable of processing multiple modalities of sensory data (e.g. video, audio) at unprecedented energy-efficiency. AI hardware architectures today cannot meet the demand due to a fundamental "memory wall": data movement between separate compute and memory units consumes large energy and incurs long latency. Resistive random-access memory (RRAM) based compute-in-memory (CIM) architectures promise to bring orders of magnitude energy-efficiency improvement by performing computation directly within memory. However, conventional approaches to CIM hardware design limit its functional flexibility necessary for processing diverse AI workloads, and must overcome hardware imperfections that degrade inference accuracy. Such trade-offs between efficiency, versatility and accuracy cannot be addressed by isolated improvements on any single level of the design. By co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM - the first multimodal edge AI chip using RRAM CIM to simultaneously deliver a high degree of versatility for diverse model architectures, record energy-efficiency $5\times$ - $8\times$ better than prior art across various computational bit-precisions, and inference accuracy comparable to software models with 4-bit weights on all measured standard AI benchmarks including accuracy of 99.0% on MNIST and 85.7% on CIFAR-10 image classification, 84.7% accuracy on Google speech command recognition, and a 70% reduction in image reconstruction error on a Bayesian image recovery task. This work paves a way towards building highly efficient and reconfigurable edge AI hardware platforms for the more demanding and heterogeneous AI applications of the future.

cs.AR↗

arXiv2021

Single-crystal hexagonal boron nitride monolayer epitaxially grown on Cu (111) thin film across a wafer

We demonstrate single crystal growth of wafer-scale hexagonal boron nitride (hBN), an insulating atomic thin monolayer, on high-symmetry index surface plane Cu(111). The unidirectional epitaxial growth is guaranteed by large binding energy difference, ~0.23 eV, between A- and B-steps edges on Cu(111) docking with B6N7 clusters, confirmed by density functional theory calculations.

cond-mat.mtrl-sci↗