ALICE Central Trigger System for LHC Run 3

Abstract

A major upgrade of the ALICE experiment is in progress and will result in high-rate data taking during LHC Run 3 (2022-2024). The LHC interaction rate at Point 2 where the ALICE experiment is located will be increased to $50\ \mathrm{kHz}$ in Pb--Pb collisions and $1\ \mathrm{MHz}$ in pp collisions. The ALICE experiment will be able to read out data at these interaction rates leading to an increase of the collected luminosity by a factor of up to about 100 with respect to LHC Runs 1 and 2. To satisfy these requirements, a new readout system has been developed for most of the ALICE detectors, allowing the full readout of the data at the required interaction rates without the need for a hardware trigger selection. A novel trigger and timing distribution system will be implemented, based on Passive Optical Network (PON) and GigaBit Transceiver (GBT) technology. To assure backward compatibility a triggered mode based on RD12 Trigger-Timing-Control (TTC) technology, as used in the previous LHC runs, will be maintained and re-implemented under the new Central Trigger System (CTS). A new universal ALICE Trigger Board (ATB) based on the Xilinx Kintex Ultrascale FPGA has been designed to function as a Central Trigger Processor (CTP), Local Trigger Unit (LTU), and monitoring interfaces. In this paper, this new hybrid multilevel system with continuous readout will be described, together with the triggering mechanism and algorithms. An overview of the CTS, the design of the ATB and the different communication protocols will be presented.