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arXiv · 2111.01369

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process

Michihiro Shintani·Riaz-Ul-Haque Mian·Tomoki Nakamura·Masuo Kajiyama·Makoto Eiki·Michiko Inoue
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Abstract

Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.

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Michihiro Shintani, Riaz-Ul-Haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue. 2021-11-02. Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. https://arxiv.org/abs/2111.01369

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