High Rate Studies of the ATLAS sTGC Detector and Optimization of the Filter Circuit on the Input of the Front-End Amplifier

Abstract

The Large Hadron Collider (LHC) at CERN is expected to be upgraded to the High-Luminosity LHC (HL-LHC) by 2029 and achieve instantaneous luminosity around 5 - 7.5 $\times$ 10$^{34}$cm$^{-2}$ s$^{-1}$. This represents a more than 3-4 fold increase in the instantaneous luminosity compared to what has been achieved in Run 2. The New Small Wheel (NSW) upgrade is designed to be able to operate efficiently in this high background rate environment. In this article, we summarize multiple performance studies of the small-strip Thin Gap Chamber (sTGC) at high rate using nearly final front-end electronics. We demonstrate that the efficiency versus rate distribution can be well described by an exponential decay with electronics dead-time being the primary cause of loss of efficiency at high rate. We then demonstrate several methods that can decrease the electronics dead-time and therefore minimize efficiency loss. One such method is to install either a pi-network input filter or pull-up resistor to minimize the charge input into the amplifier. We optimized the pi-network capacitance and pull-up resistor resistance using the results from our measurements. The results shown here were not only critical to finalizing the components on the front-end board, but also are critical for setting the optimal operating parameters of the sTGC detector and electronics in the ATLAS cavern.