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arXiv · 2406.13967

Hardware-Efficient Randomized Compiling

Neelay Fruitwala·Akel Hashim·Abhi D. Rajagopala·Yilun Xu·Jordan Hines·Ravi K. Naik·Irfan Siddiqi·Katherine Klymko·Gang Huang·Kasra Nowrouzi
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Abstract

Randomized compiling (RC) is an efficient method for tailoring arbitrary Markovian errors into stochastic Pauli channels. However, the standard procedure for implementing the protocol in software comes with a large experimental overhead -- namely, it scales linearly in the number of desired randomizations, each of which must be generated and measured independently. In this work, we introduce a hardware-efficient algorithm for performing RC on a cycle-by-cycle basis on the lowest level of our FPGA-based control hardware during the execution of a circuit. Importantly, this algorithm performs a different randomization per shot with zero runtime overhead beyond measuring a circuit without RC. We implement our algorithm using the QubiC control hardware, where we demonstrate significant reduction in the overall runtime of circuits implemented with RC, as well as a significantly lower variance in measured observables.

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Neelay Fruitwala, Akel Hashim, Abhi D. Rajagopala, Yilun Xu, Jordan Hines, Ravi K. Naik, Irfan Siddiqi, Katherine Klymko, Gang Huang, Kasra Nowrouzi. 2024-06-20. Hardware-Efficient Randomized Compiling. https://arxiv.org/abs/2406.13967

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