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arXiv · 2505.03762

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture

Riccardo Tedeschi·Gianmarco Ottavi·Côme Allart·Nils Wistoff·Zexin Fu·Filippo Grillotti·Fabio De Ambroggi·Elio Guidetti·Jean-Baptiste Rigaud·Olivier Potin·Jean Roch Coulon·César Fuguet·Luca Benini·Davide Rossi
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Abstract

Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem.

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Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart, Nils Wistoff, Zexin Fu, Filippo Grillotti, Fabio De Ambroggi, Elio Guidetti, Jean-Baptiste Rigaud, Olivier Potin, Jean Roch Coulon, César Fuguet, Luca Benini, Davide Rossi. 2025-04-20. CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. https://arxiv.org/abs/2505.03762

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