arXiv subjects

Spyros Stathopoulos

Publications and source records attributed to Spyros Stathopoulos.

18 recordsLinked to original sources

arXiv2026

A relational fabrication-to-modeling database for memristor devices

Resistive random access memory (RRAM) devices, also known as memristors, are highly dependent on fabrication, location on the wafer, and measurement protocols. However, openly available large-scale memristor datasets remain scarce, particularly those that combine experimental metadata with electrical measurements and preserve explicit links across the experimental workflow. Here, we present a comprehensive relational database of automated electrical characterization data from oxide-based memristors. The database links 6,190 memristor devices across TiN/HfOx/TiN, Pt/TiOx/AlOy/Pt, and Pt/TiOx/Pt stacks to 161,006 validated experiments and over 169 million electrical point records. It integrates fabrication, wafer mapping, electrical characterization, and modeling to describe electroforming, current-voltage non-linearity, memory windows (R_off/R_on), switching dynamics, and short-term volatility. Released as a normalized and indexed SQLite database with schema documentation, graphical user interfaces, and examples of empirical modeling, this resource supports provenance-aware querying, statistical analysis, and data-driven applications for the development of future memristor technologies.

cond-mat.mtrl-sci↗

arXiv2026

Parallel Spatial Photonic Programming of Optoelectronic IGZO RRAM with a compact $\mu$LED Array

Optoelectronic resistive random-access memory elements (ORRAM) are critical emerging devices that leverage photonic technologies to bring the advantages of optical programming to traditionally electronic memristive platforms for neuromorphic computing and artificial intelligence. In this work, a free-space optic micro-LED ($\mu$LED) array is combined with a 2-terminal oxide semiconductor ORRAM (based on IGZO\textsubscript{Rich}/IGZO active layers), to realise parallel spatial programming of form-free memristive arrays. We report the optical and electrical programming of resistive states with potentiation/depression analysis of various stimuli parameters (pulse frequency, pulse width, pulse amplitude). Further, we demonstrate the simultaneous photonic-electronic programming of the ORRAM with optical SET (blue 450\,nm) and electrical RESET functionality. Persistent photocurrent is also observed and exploited as a pathway to fading memory or synaptic plasticity for temporal bit encoding. Finally, parallel optical $\mu$LED to ORRAM channels are demonstrated to achieve the simultaneous photonic programming of multiple devices and the writing of spatial patterns across a chip of memristive IGZO devices. This work highlights the light-enabled scalability of the optoelectronic platform and the feasibility of ORRAM to interface with spatially-multiplexed optical sources to bring neuromorphic technologies directly into applications that process and sense in the optical domain.

physics.optics↗

arXiv2026

Non-frontal face recognition using GANs and memristor-based classifiers

Face recognition systems have advanced significantly through deep learning techniques, delivering high performance and robustness in complex scenarios. However, these approaches incur substantial computational overhead, limiting their in situ applicability in resource-constrained platforms such as drones, where they can address challenges including non-frontal facial imagery. Memristor-based neuromorphic systems have emerged as a compelling approach for edge AI applications, combining biologically inspired processing with efficient and scalable computation. In this work, we propose a facial recognition framework that addresses non-frontal pose variations by integrating lightweight generative adversarial network (GAN)-based pose frontalisation with memristor-based neuromorphic recognition. The experimental results on two datasets demonstrate the effectiveness of combining adversarial learning with memristive technology, achieving up to 96% identification accuracy. The proposed approach alleviates the computational bottlenecks of conventional AI and offers a scalable, efficient solution for face recognition in dynamic real-world environments.

cs.CV↗

arXiv2025

A Rapid-prototyping CMOS-RRAM Integration Strategy

Moore's law has long served the semiconductor industry as the driving force for producing ever-advancing electronics technologies. However, given the economic implications and technological challenges associated with the present semiconductor scaling constraints, a shift from a traditional more Moore approach to a beyond Moore paradigm is desirable for sustaining the current pace of innovation beyond the established development route. Resistive random-access memories (RRAM) are one such beyond Moore technology that offers many avenues for innovation, and when integrated with mature complementary metal oxide semiconductors (CMOS), can extend CMOS capabilities in a scalable and power-efficient manner, both in terms of memory and computation. Nevertheless, as emerging and established technologies fuse, existing semiconductor-optimised manufacturing faces significant challenges, while the methodologies and complexities of integration are often not highlighted in depth, or overlooked at the expense of demonstrating the application-specific integrated-technologies. In this article, we focus on the integration, and detail a cost-effective, rapid-prototyping, and technology agnostic CMOS-RRAM integration strategy that employs hybridised wafer-level and multi-reticle processing techniques, supported by a systematic increased complexity approach. Leveraging the fact that CMOS technologies can be readily realised by taking advantage of mature front-end-of-line fabrication processes offered by semiconductor foundries, we establish an in-house RRAM development program that allows to combine fundamental material and device-level knowledge with custom-designed CMOS electronics. This approach utilises fully CMOS-compatible and transferable processes, ultimately enabling a seamless transition from research and development to volume production.

cond-mat.mtrl-sci↗

arXiv2025

A Multi-Channel Auditory Signal Encoder with Adaptive Resolution Using Volatile Memristors

We demonstrate and experimentally validate an end-to-end hybrid CMOS-memristor auditory encoder that realises adaptive-threshold, asynchronous delta-modulation (ADM)-based spike encoding by exploiting the inherent volatility of HfTiOx devices. A spike-triggered programming pulse rapidly raises the ADM threshold Delta (desensitisation); the device's volatility then passively lowers Delta when activity subsides (resensitisation), emphasising onsets while restoring sensitivity without static control energy. Our prototype couples an 8-channel 130 nm encoder IC to off-chip HfTiOx devices via a switch interface and an off-chip controller that monitors spike activity and issues programming events. An on-chip current-mirror transimpedance amplifier (TIA) converts device current into symmetric thresholds, enabling both sensitive and conservative encoding regimes. Evaluated with gammatone-filtered speech, the adaptive loop-at matched spike budget-sharpens onsets and preserves fine temporal detail that a fixed-Delta baseline misses; multi-channel spike cochleagrams show the same trend. Together, these results establish a practical hybrid CMOS-memristor pathway to onset-salient, spike-efficient neuromorphic audio front-ends and motivate low-power single-chip integration.

eess.AS↗

arXiv2025

Multibit Ferroelectric Memcapacitor for Non-volatile Analogue Memory and Reconfigurable Filtering

Tuneable capacitors are vital for adaptive and reconfigurable electronics, yet existing approaches require continuous bias or mechanical actuation. Here we demonstrate a voltage-programmable ferroelectric memcapacitor based on HfZrO that achieves more than eight stable, reprogrammable capacitance states (3-bit encoding) within a non-volatile window of 24~pF. The device switches at low voltages (3~V), with each state exhibiting long retention (10^5~s) and high endurance (10^6 cycles), ensuring reliable multi-level operation. At the nanoscale, multistate charge retention was directly visualised using atomic force microscopy, confirming the robustness of individual states beyond macroscopic measurements. As a proof of concept, the capacitor was integrated into a high-pass filter, where the programmed capacitive states shift the cutoff frequency over 5~kHz, establishing circuit-level viability. This work demonstrates the feasibility of CMOS-compatible, non-volatile, analogue memory based on ferroelectric HfZrO, paving the way for adaptive RF filters, reconfigurable analogue front-ends, and neuromorphic electronics.

cond-mat.mtrl-sci↗

arXiv2022

Text Classification in Memristor-based Spiking Neural Networks

Memristors, emerging non-volatile memory devices, have shown promising potential in neuromorphic hardware designs, especially in spiking neural network (SNN) hardware implementation. Memristor-based SNNs have been successfully applied in a wide range of various applications, including image classification and pattern recognition. However, implementing memristor-based SNNs in text classification is still under exploration. One of the main reasons is that training memristor-based SNNs for text classification is costly due to the lack of efficient learning rules and memristor non-idealities. To address these issues and accelerate the research of exploring memristor-based spiking neural networks in text classification applications, we develop a simulation framework with a virtual memristor array using an empirical memristor model. We use this framework to demonstrate a sentiment analysis task in the IMDB movie reviews dataset. We take two approaches to obtain trained spiking neural networks with memristor models: 1) by converting a pre-trained artificial neural network (ANN) to a memristor-based SNN, or 2) by training a memristor-based SNN directly. These two approaches can be applied in two scenarios: offline classification and online training. We achieve the classification accuracy of 85.88% by converting a pre-trained ANN to a memristor-based SNN and 84.86% by training the memristor-based SNN directly, given that the baseline training accuracy of the equivalent ANN is 86.02%. We conclude that it is possible to achieve similar classification accuracy in simulation from ANNs to SNNs and from non-memristive synapses to data-driven memristive synapses. We also investigate how global parameters such as spike train length, the read noise, and the weight updating stop conditions affect the neural networks in both approaches.

cs.NE↗

arXiv2022

A tool for emulating neuromorphic architectures with memristive models and devices

Memristors have shown promising features for enhancing neuromorphic computing concepts and AI hardware accelerators. In this paper, we present a user-friendly software infrastructure that allows emulating a wide range of neuromorphic architectures with memristor models. This tool empowers studies that exploit memristors for online learning and online classification tasks, predicting memristor resistive state changes during the training process. The versatility of the tool is showcased through the capability for users to customise parameters in the employed memristor and neuronal models as well as the employed learning rules. This further allows users to validate concepts and their sensitivity across a wide range of parameters. We demonstrate the use of the tool via an MNIST classification task. Finally, we show how this tool can also be used to emulate the concepts under study in-silico with practical memristive devices via appropriate interfacing with commercially available characterisation tools.

cs.NE↗

arXiv2022

A CMOS-based Characterisation Platform for Emerging RRAM Technologies

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device's resistance range to be between 1k$Ω$ and 10M$Ω$ with a minimum voltage range of $\pm$1.5V on the device.

cs.ET↗

arXiv2022

Selectively biased tri-terminal vertically-integrated memristor configuration

Memristors, when utilized as electronic components in circuits, can offer opportunities for the implementation of novel reconfigurable electronics. While they have been used in large arrays, studies in ensembles of devices are comparatively limited. Here we propose a vertically stacked memristor configuration with a shared middle electrode. We study the compound resistive states presented by the combined in-series devices and we alter them either by controlling each device separately, or by altering the full configuration, which depends on selective usage of the middle floating electrode. The shared middle electrode enables a rare look into the combined system, which is not normally available in vertically stacked devices. In the course of this study it was found that separate switching of individual devices carries over its effects to the complete device (albeit non-linearly), enabling increased resistive state range, which leads to a larger number of distinguishable states (above SNR variance limits) and hence enhanced device memory. Additionally, by applying a switching stimulus to the external electrodes it is possible to switch both devices simultaneously, making the entire configuration a voltage divider with individual memristive components. Through usage of this type of configuration and by taking advantage of the voltage division, it is possible to surge-protect fragile devices, while it was also found that simultaneous reset of stacked devices is possible, significantly reducing the required reset time in larger arrays.

physics.app-ph↗

arXiv2022

NeuroPack: An Algorithm-level Python-based Simulator for Memristor-empowered Neuro-inspired Computing

Emerging two terminal nanoscale memory devices, known as memristors, have over the past decade demonstrated great potential for implementing energy efficient neuro-inspired computing architectures. As a result, a wide-range of technologies have been developed that in turn are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors' attributes in novel neuro-inspired topologies. In this paper, we present NeuroPack, a modular, algorithm level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to chose from a variety of neuron models, learning rules and memristors models. Its hierarchical structure, empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameters options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.

cs.ET↗

arXiv2022

An FPGA-based System for Generalised Electron Devices Testing

Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R&D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit (SMU), and 2x banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain $170 pA$ current noise floor, $40 ns$ pulse delivery at $\pm13.5 V$ and $12 mA$ maximum current drive/channel. We then showcase the instrument's use in performing a selection of three characteristic measurement tasks: a) current-voltage (IV) characterisation of a diode and a transistor, b) fully parallel read-out of a memristor crossbar array and c) an integral non-linearity (INL) test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies.

eess.SP↗

arXiv2021

Hybrid CMOS/Memristor Circuit Design Methodology

RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

cs.ET↗

arXiv2021

Emulating homoeostatic effects with metal-oxide memristors T-dependence

Memristor technologies have been rapidly maturing for the past decade to support the needs of emerging memory, artificial synapses, logic gates and bio-signal processing applications. So far, however, most concepts are developed by exploiting the tuneable resistive state of memristors with other physical characteristics being ignored. Here, we report on the thermal properties of metal-oxide memristors and demonstrate how these can be used to emulate a fundamental function of biological neurons: homeostasis. We show that thermal control mechanisms, frequently dismissed for their generally slow and broad-brush granularity, may in fact be an appropriate approach to emulating similarly slow and broad-brush biological mechanisms due to their extreme simplicity of implementation. We further demonstrate that metal-oxide memristors can be utilised as thermometers and exhibit a programmable temperature sensitivity. This work paves the way towards future systems that employ the rich physical properties of memristors, beyond their electrical state-tuneability, to power a new generation of advanced electronic devices.

cs.ET↗

arXiv2021

Palimpsest Memories Stored in Memristive Synapses

Biological synapses store multiple memories on top of each other in a palimpsest fashion and at different timescales. Palimpsest consolidation is facilitated by the interaction of hidden biochemical processes that govern synaptic efficacy during varying lifetimes. This arrangement allows idle memories to be temporarily overwritten without being forgotten, in favour of new memories utilised in the short-term. While embedded artificial intelligence can greatly benefit from such functionality, a practical demonstration in hardware is still missing. Here, we show how the intrinsic properties of metal-oxide volatile memristors emulate the hidden processes that support biological palimpsest consolidation. Our memristive synapses exhibit an expanded doubled capacity which can protect a consolidated long-term memory while up to hundreds of uncorrelated short-term memories temporarily overwrite it. The synapses can also implement familiarity detection of previously forgotten memories. Crucially, palimpsest operation is achieved automatically and without the need for specialised instructions. We further demonstrate a practical adaptation of this technology in the context of image vision. This showcases the use of emerging memory technologies to efficiently expand the capacity of artificial intelligence hardware towards more generalised learning memories.

q-bio.NC↗

arXiv2020

Frequency Response of Metal-Oxide Memristors

Memristors have been at the forefront of nanoelectronics research for the last decade, offering a valuable component to reconfigurable computing. Their attributes have been studied extensively along with applications that leverage their state-dependent programmability in a static fashion. However, practical applications of memristor-based AC circuits have been rather sparse, with only a few examples found in the literature where their use is emulated at higher frequencies. In this work, we study the behavior of metal-oxide memristors under an AC perturbation in a range of frequencies, from 10^3 to 10^7 Hz. Metal-oxide memristors are found to behave as RC low-pass filters and they present a variable cut-off frequency when their state is switched, thus providing a window of reconfigurability when used as filters. We further study this behaviour across distinct material systems and we show that the usable reconfigurability window of the devices can be tailored to encompass specific frequency ranges by amending the devices' capacitance. This study extends current knowledge on metal-oxide memristors by characterising their frequency dependent characteristics, providing useful insights for their use in reconfigurable AC circuits.

physics.app-ph↗

arXiv2018

A technology agnostic RRAM characterisation methodology protocol

The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and affordable and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of standard characterisation protocols for fair benchmarking. At the same time, opportunities for innovation are missed by focusing on excessively narrow performance aspects. To that end our work presents a complete, technology agnostic, characterisation methodology based on established techniques that are adapted to memristors/RRAM characterisation needs. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to benchmarking across a variety of electrical performance metrics that can in turn support the generation of device models.

physics.app-ph↗

arXiv2017

Multibit memory operation of metal-oxide bi-layer memristors

In this work, we evaluate a multitude of metal-oxide bi-layers and demonstrate the benefits from increased memory stability via multibit memory operation. We introduce a programming methodology that allows for operating metal-oxide memristive devices as multibit memory elements with highly packed yet clearly discernible memory states. We finally demonstrate a 5.5-bit memory cell (47 resistive states) with excellent retention and power consumption performance. This paves the way for neuromorphic and non-volatile memory applications.

cond-mat.mes-hall↗